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commit 864016ce6169d3909ff90942e802c8a931f9d35c
parent 8839e907e3147d1e22bcd69001f9ee768fc84ed5
Author: Rong "Mantle" Bao <webmaster@csmantle.top>
Date:   Thu, 18 Dec 2025 20:33:55 +0000

Bug 2005120 - [riscv64] Part 2: (Drive-by) Rename Zb* assembler functions to existing naming convention. r=m_kato,spidermonkey-reviewers,iain

Existing functions uses an underscore to replace the dots in instruction
mnemonics to form a valid C identifier. This patch renames newly-added
functions to match this convention.

Differential Revision: https://phabricator.services.mozilla.com/D276404

Diffstat:
M
js/src/jit/riscv64/MacroAssembler-riscv64.h
 | 
6
+++---
M
js/src/jit/riscv64/extension/extension-riscv-b.cc
 | 
18
+++++++++---------
M
js/src/jit/riscv64/extension/extension-riscv-b.h
 | 
20
++++++++++----------

3 files changed, 22 insertions(+), 22 deletions(-)
diff --git a/js/src/jit/riscv64/MacroAssembler-riscv64.h b/js/src/jit/riscv64/MacroAssembler-riscv64.h
@@ -1072,7 +1072,7 @@ class MacroAssemblerRiscv64Compat : public MacroAssemblerRiscv64 {
 
   void SignExtendByte(Register rd, Register rs) {
     if (HasZbbExtension()) {
-      sextb(rd, rs);
+      sext_b(rd, rs);
       return;
     }
     slli(rd, rs, xlen - 8);
@@ -1081,7 +1081,7 @@ class MacroAssemblerRiscv64Compat : public MacroAssemblerRiscv64 {
 
   void SignExtendShort(Register rd, Register rs) {
     if (HasZbbExtension()) {
-      sexth(rd, rs);
+      sext_h(rd, rs);
       return;
     }
     slli(rd, rs, xlen - 16);
@@ -1091,7 +1091,7 @@ class MacroAssemblerRiscv64Compat : public MacroAssemblerRiscv64 {
   void SignExtendWord(Register rd, Register rs) { sext_w(rd, rs); }
   void ZeroExtendWord(Register rd, Register rs) {
     if (HasZbaExtension()) {
-      zextw(rd, rs);
+      zext_w(rd, rs);
       return;
     }
     slli(rd, rs, 32);
diff --git a/js/src/jit/riscv64/extension/extension-riscv-b.cc b/js/src/jit/riscv64/extension/extension-riscv-b.cc
@@ -21,19 +21,19 @@ void AssemblerRISCVB::sh3add(Register rd, Register rs1, Register rs2) {
   GenInstrALU_rr(0b0010000, 0b110, rd, rs1, rs2);
 }
 #ifdef JS_CODEGEN_RISCV64
-void AssemblerRISCVB::adduw(Register rd, Register rs1, Register rs2) {
+void AssemblerRISCVB::add_uw(Register rd, Register rs1, Register rs2) {
   GenInstrALUW_rr(0b0000100, 0b000, rd, rs1, rs2);
 }
-void AssemblerRISCVB::sh1adduw(Register rd, Register rs1, Register rs2) {
+void AssemblerRISCVB::sh1add_uw(Register rd, Register rs1, Register rs2) {
   GenInstrALUW_rr(0b0010000, 0b010, rd, rs1, rs2);
 }
-void AssemblerRISCVB::sh2adduw(Register rd, Register rs1, Register rs2) {
+void AssemblerRISCVB::sh2add_uw(Register rd, Register rs1, Register rs2) {
   GenInstrALUW_rr(0b0010000, 0b100, rd, rs1, rs2);
 }
-void AssemblerRISCVB::sh3adduw(Register rd, Register rs1, Register rs2) {
+void AssemblerRISCVB::sh3add_uw(Register rd, Register rs1, Register rs2) {
   GenInstrALUW_rr(0b0010000, 0b110, rd, rs1, rs2);
 }
-void AssemblerRISCVB::slliuw(Register rd, Register rs1, uint8_t shamt) {
+void AssemblerRISCVB::slli_uw(Register rd, Register rs1, uint8_t shamt) {
   GenInstrIShift(0b000010, 0b001, OP_IMM_32, rd, rs1, shamt);
 }
 #endif  // JS_CODEGEN_RISCV64
@@ -82,13 +82,13 @@ void AssemblerRISCVB::minu(Register rd, Register rs1, Register rs2) {
   GenInstrALU_rr(0b0000101, 0b101, rd, rs1, rs2);
 }
 
-void AssemblerRISCVB::sextb(Register rd, Register rs) {
+void AssemblerRISCVB::sext_b(Register rd, Register rs) {
   GenInstrIShiftW(0b0110000, 0b001, OP_IMM, rd, rs, 0b100);
 }
-void AssemblerRISCVB::sexth(Register rd, Register rs) {
+void AssemblerRISCVB::sext_h(Register rd, Register rs) {
   GenInstrIShiftW(0b0110000, 0b001, OP_IMM, rd, rs, 0b101);
 }
-void AssemblerRISCVB::zexth(Register rd, Register rs) {
+void AssemblerRISCVB::zext_h(Register rd, Register rs) {
 #ifdef JS_CODEGEN_RISCV64
   GenInstrALUW_rr(0b0000100, 0b100, rd, rs, zero_reg);
 #else
@@ -104,7 +104,7 @@ void AssemblerRISCVB::ror(Register rd, Register rs1, Register rs2) {
   GenInstrR(0b0110000, 0b101, OP, rd, rs1, rs2);
 }
 
-void AssemblerRISCVB::orcb(Register rd, Register rs) {
+void AssemblerRISCVB::orc_b(Register rd, Register rs) {
   GenInstrI(0b101, OP_IMM, rd, rs, 0b001010000111);
 }
 
diff --git a/js/src/jit/riscv64/extension/extension-riscv-b.h b/js/src/jit/riscv64/extension/extension-riscv-b.h
@@ -20,12 +20,12 @@ class AssemblerRISCVB : public AssemblerRiscvBase {
   void sh2add(Register rd, Register rs1, Register rs2);
   void sh3add(Register rd, Register rs1, Register rs2);
 #ifdef JS_CODEGEN_RISCV64
-  void adduw(Register rd, Register rs1, Register rs2);
-  void zextw(Register rd, Register rs1) { adduw(rd, rs1, zero_reg); }
-  void sh1adduw(Register rd, Register rs1, Register rs2);
-  void sh2adduw(Register rd, Register rs1, Register rs2);
-  void sh3adduw(Register rd, Register rs1, Register rs2);
-  void slliuw(Register rd, Register rs1, uint8_t shamt);
+  void add_uw(Register rd, Register rs1, Register rs2);
+  void zext_w(Register rd, Register rs1) { add_uw(rd, rs1, zero_reg); }
+  void sh1add_uw(Register rd, Register rs1, Register rs2);
+  void sh2add_uw(Register rd, Register rs1, Register rs2);
+  void sh3add_uw(Register rd, Register rs1, Register rs2);
+  void slli_uw(Register rd, Register rs1, uint8_t shamt);
 #endif
 
   // Zbb Extension
@@ -47,15 +47,15 @@ class AssemblerRISCVB : public AssemblerRiscvBase {
   void min(Register rd, Register rs1, Register rs2);
   void minu(Register rd, Register rs1, Register rs2);
 
-  void sextb(Register rd, Register rs);
-  void sexth(Register rd, Register rs);
-  void zexth(Register rd, Register rs);
+  void sext_b(Register rd, Register rs);
+  void sext_h(Register rd, Register rs);
+  void zext_h(Register rd, Register rs);
 
   // Zbb: bitwise rotation
   void rol(Register rd, Register rs1, Register rs2);
   void ror(Register rd, Register rs1, Register rs2);
   void rori(Register rd, Register rs1, uint8_t shamt);
-  void orcb(Register rd, Register rs);
+  void orc_b(Register rd, Register rs);
   void rev8(Register rd, Register rs);
 #ifdef JS_CODEGEN_RISCV64
   void rolw(Register rd, Register rs1, Register rs2);