extension-riscv-b.cc (6272B)
1 // Copyright 2022 the V8 project authors. All rights reserved. 2 // Use of this source code is governed by a BSD-style license that can be 3 // found in the LICENSE file. 4 5 #include "jit/riscv64/extension/extension-riscv-b.h" 6 #include "jit/riscv64/Assembler-riscv64.h" 7 #include "jit/riscv64/constant/Constant-riscv64.h" 8 #include "jit/riscv64/Architecture-riscv64.h" 9 10 namespace js { 11 namespace jit { 12 13 // RV32B Standard Extension 14 void AssemblerRISCVB::sh1add(Register rd, Register rs1, Register rs2) { 15 GenInstrALU_rr(0b0010000, 0b010, rd, rs1, rs2); 16 } 17 void AssemblerRISCVB::sh2add(Register rd, Register rs1, Register rs2) { 18 GenInstrALU_rr(0b0010000, 0b100, rd, rs1, rs2); 19 } 20 void AssemblerRISCVB::sh3add(Register rd, Register rs1, Register rs2) { 21 GenInstrALU_rr(0b0010000, 0b110, rd, rs1, rs2); 22 } 23 #ifdef JS_CODEGEN_RISCV64 24 void AssemblerRISCVB::add_uw(Register rd, Register rs1, Register rs2) { 25 GenInstrALUW_rr(0b0000100, 0b000, rd, rs1, rs2); 26 } 27 void AssemblerRISCVB::sh1add_uw(Register rd, Register rs1, Register rs2) { 28 GenInstrALUW_rr(0b0010000, 0b010, rd, rs1, rs2); 29 } 30 void AssemblerRISCVB::sh2add_uw(Register rd, Register rs1, Register rs2) { 31 GenInstrALUW_rr(0b0010000, 0b100, rd, rs1, rs2); 32 } 33 void AssemblerRISCVB::sh3add_uw(Register rd, Register rs1, Register rs2) { 34 GenInstrALUW_rr(0b0010000, 0b110, rd, rs1, rs2); 35 } 36 void AssemblerRISCVB::slli_uw(Register rd, Register rs1, uint8_t shamt) { 37 GenInstrIShift(0b000010, 0b001, OP_IMM_32, rd, rs1, shamt); 38 } 39 #endif // JS_CODEGEN_RISCV64 40 41 void AssemblerRISCVB::andn(Register rd, Register rs1, Register rs2) { 42 GenInstrALU_rr(0b0100000, 0b111, rd, rs1, rs2); 43 } 44 void AssemblerRISCVB::orn(Register rd, Register rs1, Register rs2) { 45 GenInstrALU_rr(0b0100000, 0b110, rd, rs1, rs2); 46 } 47 void AssemblerRISCVB::xnor(Register rd, Register rs1, Register rs2) { 48 GenInstrALU_rr(0b0100000, 0b100, rd, rs1, rs2); 49 } 50 51 void AssemblerRISCVB::clz(Register rd, Register rs) { 52 GenInstrIShiftW(0b0110000, 0b001, OP_IMM, rd, rs, 0); 53 } 54 void AssemblerRISCVB::ctz(Register rd, Register rs) { 55 GenInstrIShiftW(0b0110000, 0b001, OP_IMM, rd, rs, 1); 56 } 57 void AssemblerRISCVB::cpop(Register rd, Register rs) { 58 GenInstrIShiftW(0b0110000, 0b001, OP_IMM, rd, rs, 2); 59 } 60 #ifdef JS_CODEGEN_RISCV64 61 void AssemblerRISCVB::clzw(Register rd, Register rs) { 62 GenInstrIShiftW(0b0110000, 0b001, OP_IMM_32, rd, rs, 0); 63 } 64 void AssemblerRISCVB::ctzw(Register rd, Register rs) { 65 GenInstrIShiftW(0b0110000, 0b001, OP_IMM_32, rd, rs, 1); 66 } 67 void AssemblerRISCVB::cpopw(Register rd, Register rs) { 68 GenInstrIShiftW(0b0110000, 0b001, OP_IMM_32, rd, rs, 2); 69 } 70 #endif 71 72 void AssemblerRISCVB::max(Register rd, Register rs1, Register rs2) { 73 GenInstrALU_rr(0b0000101, 0b110, rd, rs1, rs2); 74 } 75 void AssemblerRISCVB::maxu(Register rd, Register rs1, Register rs2) { 76 GenInstrALU_rr(0b0000101, 0b111, rd, rs1, rs2); 77 } 78 void AssemblerRISCVB::min(Register rd, Register rs1, Register rs2) { 79 GenInstrALU_rr(0b0000101, 0b100, rd, rs1, rs2); 80 } 81 void AssemblerRISCVB::minu(Register rd, Register rs1, Register rs2) { 82 GenInstrALU_rr(0b0000101, 0b101, rd, rs1, rs2); 83 } 84 85 void AssemblerRISCVB::sext_b(Register rd, Register rs) { 86 GenInstrIShiftW(0b0110000, 0b001, OP_IMM, rd, rs, 0b100); 87 } 88 void AssemblerRISCVB::sext_h(Register rd, Register rs) { 89 GenInstrIShiftW(0b0110000, 0b001, OP_IMM, rd, rs, 0b101); 90 } 91 void AssemblerRISCVB::zext_h(Register rd, Register rs) { 92 #ifdef JS_CODEGEN_RISCV64 93 GenInstrALUW_rr(0b0000100, 0b100, rd, rs, zero_reg); 94 #else 95 GenInstrALU_rr(0b0000100, 0b100, rd, rs, zero_reg); 96 #endif 97 } 98 99 void AssemblerRISCVB::rol(Register rd, Register rs1, Register rs2) { 100 GenInstrR(0b0110000, 0b001, OP, rd, rs1, rs2); 101 } 102 103 void AssemblerRISCVB::ror(Register rd, Register rs1, Register rs2) { 104 GenInstrR(0b0110000, 0b101, OP, rd, rs1, rs2); 105 } 106 107 void AssemblerRISCVB::orc_b(Register rd, Register rs) { 108 GenInstrI(0b101, OP_IMM, rd, rs, 0b001010000111); 109 } 110 111 void AssemblerRISCVB::rori(Register rd, Register rs1, uint8_t shamt) { 112 #ifdef JS_CODEGEN_RISCV64 113 MOZ_ASSERT(is_uint6(shamt)); 114 GenInstrI(0b101, OP_IMM, rd, rs1, 0b011000000000 | shamt); 115 #else 116 DCHECK(is_uint5(shamt)); 117 GenInstrI(0b101, OP_IMM, rd, rs1, 0b011000000000 | shamt); 118 #endif 119 } 120 121 #ifdef JS_CODEGEN_RISCV64 122 void AssemblerRISCVB::rolw(Register rd, Register rs1, Register rs2) { 123 GenInstrR(0b0110000, 0b001, OP_32, rd, rs1, rs2); 124 } 125 void AssemblerRISCVB::roriw(Register rd, Register rs1, uint8_t shamt) { 126 MOZ_ASSERT(is_uint5(shamt)); 127 GenInstrI(0b101, OP_IMM_32, rd, rs1, 0b011000000000 | shamt); 128 } 129 void AssemblerRISCVB::rorw(Register rd, Register rs1, Register rs2) { 130 GenInstrR(0b0110000, 0b101, OP_32, rd, rs1, rs2); 131 } 132 #endif 133 134 void AssemblerRISCVB::rev8(Register rd, Register rs) { 135 #ifdef JS_CODEGEN_RISCV64 136 GenInstrI(0b101, OP_IMM, rd, rs, 0b011010111000); 137 #else 138 GenInstrI(0b101, OP_IMM, rd, rs, 0b011010011000); 139 #endif 140 } 141 142 void AssemblerRISCVB::bclr(Register rd, Register rs1, Register rs2) { 143 GenInstrALU_rr(0b0100100, 0b001, rd, rs1, rs2); 144 } 145 146 void AssemblerRISCVB::bclri(Register rd, Register rs, uint8_t shamt) { 147 #ifdef JS_CODEGEN_RISCV64 148 GenInstrIShift(0b010010, 0b001, OP_IMM, rd, rs, shamt); 149 #else 150 GenInstrIShiftW(0b0100100, 0b001, OP_IMM, rd, rs, shamt); 151 #endif 152 } 153 void AssemblerRISCVB::bext(Register rd, Register rs1, Register rs2) { 154 GenInstrALU_rr(0b0100100, 0b101, rd, rs1, rs2); 155 } 156 void AssemblerRISCVB::bexti(Register rd, Register rs1, uint8_t shamt) { 157 #ifdef JS_CODEGEN_RISCV64 158 GenInstrIShift(0b010010, 0b101, OP_IMM, rd, rs1, shamt); 159 #else 160 GenInstrIShiftW(0b0100100, 0b101, OP_IMM, rd, rs1, shamt); 161 #endif 162 } 163 void AssemblerRISCVB::binv(Register rd, Register rs1, Register rs2) { 164 GenInstrALU_rr(0b0110100, 0b001, rd, rs1, rs2); 165 } 166 void AssemblerRISCVB::binvi(Register rd, Register rs1, uint8_t shamt) { 167 #ifdef JS_CODEGEN_RISCV64 168 GenInstrIShift(0b011010, 0b001, OP_IMM, rd, rs1, shamt); 169 #else 170 GenInstrIShiftW(0b0110100, 0b001, OP_IMM, rd, rs1, shamt); 171 #endif 172 } 173 void AssemblerRISCVB::bset(Register rd, Register rs1, Register rs2) { 174 GenInstrALU_rr(0b0010100, 0b001, rd, rs1, rs2); 175 } 176 void AssemblerRISCVB::bseti(Register rd, Register rs1, uint8_t shamt) { 177 #ifdef JS_CODEGEN_RISCV64 178 GenInstrIShift(0b001010, 0b001, OP_IMM, rd, rs1, shamt); 179 #else 180 GenInstrIShiftW(0b0010100, 0b001, OP_IMM, rd, rs1, shamt); 181 #endif 182 } 183 } // namespace jit 184 } // namespace js