commit 8839e907e3147d1e22bcd69001f9ee768fc84ed5
parent 113d24b27ae7e2932e195beb80c0a0d261325a22
Author: Rong "Mantle" Bao <webmaster@csmantle.top>
Date: Thu, 18 Dec 2025 20:33:55 +0000
Bug 2005120 - [riscv64] Part 1: Simplify MacroAssemblerRiscv64Compat::ZeroExtendWord with zext.w from Zba extension. r=m_kato,spidermonkey-reviewers,iain
Differential Revision: https://phabricator.services.mozilla.com/D276403
Diffstat:
3 files changed, 16 insertions(+), 0 deletions(-)
diff --git a/js/src/jit/riscv64/Assembler-riscv64.cpp b/js/src/jit/riscv64/Assembler-riscv64.cpp
@@ -67,11 +67,18 @@ void RVFlags::Init() {
__has_include(<asm/hwprobe.h>)
riscv_hwprobe probe[1] = {{RISCV_HWPROBE_KEY_IMA_EXT_0, 0}};
if (syscall(__NR_riscv_hwprobe, probe, 1, 0, nullptr, 0) == 0) {
+ if (probe[0].value & RISCV_HWPROBE_EXT_ZBA) {
+ sZbaExtension = true;
+ }
if (probe[0].value & RISCV_HWPROBE_EXT_ZBB) {
sZbbExtension = true;
}
}
#else
+ if (getenv("RISCV_EXT_ZBA")) {
+ // Force on Zba extension for testing purposes or on non-linux platforms.
+ sZbaExtension = true;
+ }
if (getenv("RISCV_EXT_ZBB")) {
// Force on Zbb extension for testing purposes or on non-linux platforms.
sZbbExtension = true;
diff --git a/js/src/jit/riscv64/Assembler-riscv64.h b/js/src/jit/riscv64/Assembler-riscv64.h
@@ -79,9 +79,12 @@ class RVFlags final {
static bool FlagsHaveBeenComputed() { return sComputed; }
+ static bool HasZbaExtension() { return sZbaExtension; }
+
static bool HasZbbExtension() { return sZbbExtension; }
private:
+ static inline bool sZbaExtension = false;
static inline bool sZbbExtension = false;
static inline bool sComputed = false;
};
@@ -505,6 +508,8 @@ class Assembler : public AssemblerShared,
MOZ_CRASH("unexpected mode");
}
+ static bool HasZbaExtension() { return RVFlags::HasZbaExtension(); }
+
static bool HasZbbExtension() { return RVFlags::HasZbbExtension(); }
void verifyHeapAccessDisassembly(uint32_t begin, uint32_t end,
diff --git a/js/src/jit/riscv64/MacroAssembler-riscv64.h b/js/src/jit/riscv64/MacroAssembler-riscv64.h
@@ -1090,6 +1090,10 @@ class MacroAssemblerRiscv64Compat : public MacroAssemblerRiscv64 {
void SignExtendWord(Register rd, Register rs) { sext_w(rd, rs); }
void ZeroExtendWord(Register rd, Register rs) {
+ if (HasZbaExtension()) {
+ zextw(rd, rs);
+ return;
+ }
slli(rd, rs, 32);
srli(rd, rd, 32);
}