tor-browser

The Tor Browser
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commit cac175544b82b2856fd54e26f54a359e0adb6dad
parent 7cf2d8c07945c3a00a8a750edb80dab0829584d7
Author: André Bargull <andre.bargull@gmail.com>
Date:   Thu, 23 Oct 2025 11:39:52 +0000

Bug 1995594 - Part 3: Rename temporary register names to match N64. r=spidermonkey-reviewers,jandem

Differential Revision: https://phabricator.services.mozilla.com/D269436

Diffstat:
Mjs/src/jit/mips-shared/Architecture-mips-shared.h | 16++++++++--------
Mjs/src/jit/mips-shared/Assembler-mips-shared.h | 16++++++++--------
Mjs/src/jit/mips64/Architecture-mips64.cpp | 2+-
Mjs/src/jit/mips64/Assembler-mips64.h | 18+++++++++---------
Mjs/src/jit/mips64/Simulator-mips64.h | 8++++----
Mjs/src/jsapi-tests/testJitABIcalls.cpp | 2+-
Mjs/src/shell/js.cpp | 2+-
7 files changed, 32 insertions(+), 32 deletions(-)

diff --git a/js/src/jit/mips-shared/Architecture-mips-shared.h b/js/src/jit/mips-shared/Architecture-mips-shared.h @@ -82,10 +82,10 @@ class Registers { a5 = r9, a6 = r10, a7 = r11, - t0 = r12, - t1 = r13, - t2 = r14, - t3 = r15, + t4 = r12, + t5 = r13, + t6 = r14, + t7 = r15, ta0 = a4, ta1 = a5, ta2 = a6, @@ -141,8 +141,8 @@ class Registers { (1 << Registers::v0) | (1 << Registers::v1) | (1 << Registers::a0) | (1 << Registers::a1) | (1 << Registers::a2) | (1 << Registers::a3) | (1 << Registers::a4) | (1 << Registers::a5) | (1 << Registers::a6) | - (1 << Registers::a7) | (1 << Registers::t0) | (1 << Registers::t1) | - (1 << Registers::t2) | (1 << Registers::t3) | (1 << Registers::t8) | + (1 << Registers::a7) | (1 << Registers::t4) | (1 << Registers::t5) | + (1 << Registers::t6) | (1 << Registers::t7) | (1 << Registers::t8) | (1 << Registers::t9); // We use this constant to save registers when entering functions. This @@ -154,8 +154,8 @@ class Registers { (1 << Registers::ra); static const SetType WrapperMask = VolatileMask | // = arguments - (1 << Registers::t0) | // = outReg - (1 << Registers::t1); // = argBase + (1 << Registers::t4) | // = outReg + (1 << Registers::t5); // = argBase static const SetType NonAllocatableMask = (1 << Registers::zero) | (1 << Registers::at) | // at = scratch diff --git a/js/src/jit/mips-shared/Assembler-mips-shared.h b/js/src/jit/mips-shared/Assembler-mips-shared.h @@ -34,10 +34,10 @@ static constexpr Register a4{Registers::a4}; static constexpr Register a5{Registers::a5}; static constexpr Register a6{Registers::a6}; static constexpr Register a7{Registers::a7}; -static constexpr Register t0{Registers::t0}; -static constexpr Register t1{Registers::t1}; -static constexpr Register t2{Registers::t2}; -static constexpr Register t3{Registers::t3}; +static constexpr Register t4{Registers::t4}; +static constexpr Register t5{Registers::t5}; +static constexpr Register t6{Registers::t6}; +static constexpr Register t7{Registers::t7}; static constexpr Register s0{Registers::s0}; static constexpr Register s1{Registers::s1}; static constexpr Register s2{Registers::s2}; @@ -84,10 +84,10 @@ class UseScratchRegisterScope { // Use arg reg from EnterJIT function as OsrFrameReg. static constexpr Register OsrFrameReg = a3; -static constexpr Register CallTempReg0 = t0; -static constexpr Register CallTempReg1 = t1; -static constexpr Register CallTempReg2 = t2; -static constexpr Register CallTempReg3 = t3; +static constexpr Register CallTempReg0 = t4; +static constexpr Register CallTempReg1 = t5; +static constexpr Register CallTempReg2 = t6; +static constexpr Register CallTempReg3 = t7; static constexpr Register IntArgReg0 = a0; static constexpr Register IntArgReg1 = a1; diff --git a/js/src/jit/mips64/Architecture-mips64.cpp b/js/src/jit/mips64/Architecture-mips64.cpp @@ -13,7 +13,7 @@ namespace jit { const char* const Registers::RegNames[] = { "zero", "at", "v0", "v1", "a0", "a1", "a2", "a3", "a4", "a5", "a6", - "a7", "t0", "t1", "t2", "t3", "s0", "s1", "s2", "s3", "s4", "s5", + "a7", "t4", "t5", "t6", "t7", "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7", "t8", "t9", "k0", "k1", "gp", "sp", "fp", "ra"}; const uint32_t Allocatable = 22; diff --git a/js/src/jit/mips64/Assembler-mips64.h b/js/src/jit/mips64/Assembler-mips64.h @@ -19,7 +19,7 @@ namespace jit { static constexpr Register CallTempReg4 = a4; static constexpr Register CallTempReg5 = a5; -static constexpr Register CallTempNonArgRegs[] = {t0, t1, t2, t3}; +static constexpr Register CallTempNonArgRegs[] = {t4, t5, t6, t7}; static const uint32_t NumCallTempNonArgRegs = std::size(CallTempNonArgRegs); class ABIArgGenerator : public ABIArgGeneratorShared { @@ -35,10 +35,10 @@ class ABIArgGenerator : public ABIArgGeneratorShared { }; // These registers may be volatile or nonvolatile. -static constexpr Register ABINonArgReg0 = t0; -static constexpr Register ABINonArgReg1 = t1; -static constexpr Register ABINonArgReg2 = t2; -static constexpr Register ABINonArgReg3 = t3; +static constexpr Register ABINonArgReg0 = t4; +static constexpr Register ABINonArgReg1 = t5; +static constexpr Register ABINonArgReg2 = t6; +static constexpr Register ABINonArgReg3 = t7; // This register may be volatile or nonvolatile. Avoid f23 which is the // ScratchDoubleReg. @@ -47,14 +47,14 @@ static constexpr FloatRegister ABINonArgDoubleReg{FloatRegisters::f21, // These registers may be volatile or nonvolatile. // Note: these three registers are all guaranteed to be different -static constexpr Register ABINonArgReturnReg0 = t0; -static constexpr Register ABINonArgReturnReg1 = t1; +static constexpr Register ABINonArgReturnReg0 = t4; +static constexpr Register ABINonArgReturnReg1 = t5; static constexpr Register ABINonVolatileReg = s0; // This register is guaranteed to be clobberable during the prologue and // epilogue of an ABI call which must preserve both ABI argument, return // and non-volatile registers. -static constexpr Register ABINonArgReturnVolatileReg = t0; +static constexpr Register ABINonArgReturnVolatileReg = t4; // TLS pointer argument register for WebAssembly functions. This must not alias // any other register used for passing function arguments or return values. @@ -82,7 +82,7 @@ static constexpr Register WasmTailCallFPScratchReg = ABINonArgReg3; // Register used as a scratch along the return path in the fast js -> wasm stub // code. This must not overlap ReturnReg, JSReturnOperand, or InstanceReg. // It must be a volatile register. -static constexpr Register WasmJitEntryReturnScratch = t1; +static constexpr Register WasmJitEntryReturnScratch = t5; static constexpr Register InterpreterPCReg = a5; diff --git a/js/src/jit/mips64/Simulator-mips64.h b/js/src/jit/mips64/Simulator-mips64.h @@ -139,10 +139,10 @@ class Simulator { a5, a6, a7, - t0, - t1, - t2, - t3, + t4, + t5, + t6, + t7, s0, s1, s2, diff --git a/js/src/jsapi-tests/testJitABIcalls.cpp b/js/src/jsapi-tests/testJitABIcalls.cpp @@ -713,7 +713,7 @@ class JitABICall final : public JSAPIRuntimeTest, public DefineCheckArgs<Sig> { Register base = r8; regs.take(base); #elif defined(JS_CODEGEN_MIPS64) - Register base = t1; + Register base = t5; regs.take(base); #elif defined(JS_CODEGEN_LOONG64) Register base = t0; diff --git a/js/src/shell/js.cpp b/js/src/shell/js.cpp @@ -7810,7 +7810,7 @@ static void SingleStepCallback(void* arg, jit::Simulator* sim, void* pc) { state.lr = (void*)sim->getRegister(jit::Simulator::ra); state.fp = (void*)sim->getRegister(jit::Simulator::fp); // see WasmTailCallFPScratchReg and CollapseWasmFrameFast - state.tempFP = (void*)sim->getRegister(jit::Simulator::t3); + state.tempFP = (void*)sim->getRegister(jit::Simulator::t7); # elif defined(JS_SIMULATOR_LOONG64) state.sp = (void*)sim->getRegister(jit::Simulator::sp); state.lr = (void*)sim->getRegister(jit::Simulator::ra);