tor-browser

commit f626051b39941931dcfa232c9e7a43ae1c3e6127
parent 45067641a270b705ec741af9b4fc653591981d5e
Author: André Bargull <andre.bargull@gmail.com>
Date:   Tue,  4 Nov 2025 16:00:48 +0000

Bug 1997867: Improve disassembly for Wasm trap instruction. r=spidermonkey-reviewers,iain

Disassembly for Wasm traps currently emits:
```
d4a00000        unimplemented (Exception)
```

With this patch disassembly changes to:
```
d4a00000  dcps0   {#0x0} (Wasm Trap)
```

Differential Revision: https://phabricator.services.mozilla.com/D271014

Diffstat:
M
js/src/jit-test/tests/wasm/builtin-modules/js-string/inline-code.js
 | 
2
+-
M
js/src/jit/arm64/vixl/Constants-vixl.h
 | 
8
++++++--
M
js/src/jit/arm64/vixl/Disasm-vixl.cpp
 | 
1
+

3 files changed, 8 insertions(+), 3 deletions(-)
diff --git a/js/src/jit-test/tests/wasm/builtin-modules/js-string/inline-code.js b/js/src/jit-test/tests/wasm/builtin-modules/js-string/inline-code.js
@@ -30,6 +30,6 @@ codegenTestARM64_adhoc(`
   `and     x1, x0, #0x3
   cmp     w1, #0x2 \\(2\\)
   b.eq    #\\+0x8 \\(addr .*\\)
-  unimplemented \\(Exception\\)`,
+  dcps0   \\{#0x0\\} \\(Wasm Trap\\)`,
   {features: {builtins: ["js-string"]}}
 );
diff --git a/js/src/jit/arm64/vixl/Constants-vixl.h b/js/src/jit/arm64/vixl/Constants-vixl.h
@@ -1005,7 +1005,11 @@ enum ExceptionOp : uint32_t {
   SMC            = ExceptionFixed | 0x00000003,
   DCPS1          = ExceptionFixed | 0x00A00001,
   DCPS2          = ExceptionFixed | 0x00A00002,
-  DCPS3          = ExceptionFixed | 0x00A00003
+  DCPS3          = ExceptionFixed | 0x00A00003,
+
+  // Mozilla change:
+  // Add pseudo-instruction for Wasm traps.
+  DCPS0          = ExceptionFixed | 0x00A00000,
 };
 
 enum MemBarrierOp : uint32_t {
@@ -4557,7 +4561,7 @@ enum MaxMinImmediateOp : uint32_t {
 // 0x5ac00c00 (rbit variant)
 //
 // This instruction is "dcps0", also has 16-bit payload if needed.
-static constexpr uint32_t UNDEFINED_INST_PATTERN = 0xd4a00000;
+static constexpr uint32_t UNDEFINED_INST_PATTERN = DCPS0;
 
 }  // namespace vixl
 
diff --git a/js/src/jit/arm64/vixl/Disasm-vixl.cpp b/js/src/jit/arm64/vixl/Disasm-vixl.cpp
@@ -1628,6 +1628,7 @@ void Disassembler::VisitException(const Instruction* instr) {
     case SVC: mnemonic = "svc"; break;
     case HVC: mnemonic = "hvc"; break;
     case SMC: mnemonic = "smc"; break;
+    case DCPS0: mnemonic = "dcps0"; form = "{'IDebug} (Wasm Trap)"; break;
     case DCPS1: mnemonic = "dcps1"; form = "{'IDebug}"; break;
     case DCPS2: mnemonic = "dcps2"; form = "{'IDebug}"; break;
     case DCPS3: mnemonic = "dcps3"; form = "{'IDebug}"; break;