Constants-vixl.h (207564B)
1 // Copyright 2015, VIXL authors 2 // All rights reserved. 3 // 4 // Redistribution and use in source and binary forms, with or without 5 // modification, are permitted provided that the following conditions are met: 6 // 7 // * Redistributions of source code must retain the above copyright notice, 8 // this list of conditions and the following disclaimer. 9 // * Redistributions in binary form must reproduce the above copyright notice, 10 // this list of conditions and the following disclaimer in the documentation 11 // and/or other materials provided with the distribution. 12 // * Neither the name of ARM Limited nor the names of its contributors may be 13 // used to endorse or promote products derived from this software without 14 // specific prior written permission. 15 // 16 // THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS CONTRIBUTORS "AS IS" AND 17 // ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 18 // WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 19 // DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE 20 // FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 21 // DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 22 // SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER 23 // CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 24 // OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 25 // OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 26 27 #ifndef VIXL_A64_CONSTANTS_A64_H_ 28 #define VIXL_A64_CONSTANTS_A64_H_ 29 30 #include <stdint.h> 31 32 #include "jit/arm64/vixl/Globals-vixl.h" 33 34 namespace vixl { 35 36 // Supervisor Call (svc) specific support. 37 // 38 // The SVC instruction encodes an optional 16-bit immediate value. 39 // The simulator understands the codes below. 40 enum SVCSimulatorCodes { 41 kCallRtRedirected = 0x10, // Transition to x86_64 C code. 42 kMarkStackPointer = 0x11, // Push the current SP on a special Simulator stack. 43 kCheckStackPointer = 0x12 // Pop from the special Simulator stack and compare to SP. 44 }; 45 46 const unsigned kNumberOfRegisters = 32; 47 const unsigned kNumberOfVRegisters = 32; 48 const unsigned kNumberOfFPRegisters = kNumberOfVRegisters; 49 const unsigned kNumberOfZRegisters = kNumberOfVRegisters; 50 const unsigned kNumberOfPRegisters = 16; 51 // Callee saved registers are x21-x30(lr). 52 const int kNumberOfCalleeSavedRegisters = 10; 53 const int kFirstCalleeSavedRegisterIndex = 21; 54 // Callee saved FP registers are d8-d15. Note that the high parts of v8-v15 are 55 // still caller-saved. 56 const int kNumberOfCalleeSavedFPRegisters = 8; 57 const int kFirstCalleeSavedFPRegisterIndex = 8; 58 // All predicated instructions accept at least p0-p7 as the governing predicate. 59 const unsigned kNumberOfGoverningPRegisters = 8; 60 61 // clang-format off 62 #define AARCH64_P_REGISTER_CODE_LIST(R) \ 63 R(0) R(1) R(2) R(3) R(4) R(5) R(6) R(7) \ 64 R(8) R(9) R(10) R(11) R(12) R(13) R(14) R(15) 65 66 #define AARCH64_REGISTER_CODE_LIST(R) \ 67 R(0) R(1) R(2) R(3) R(4) R(5) R(6) R(7) \ 68 R(8) R(9) R(10) R(11) R(12) R(13) R(14) R(15) \ 69 R(16) R(17) R(18) R(19) R(20) R(21) R(22) R(23) \ 70 R(24) R(25) R(26) R(27) R(28) R(29) R(30) R(31) 71 72 #define REGISTER_CODE_LIST(R) \ 73 R(0) R(1) R(2) R(3) R(4) R(5) R(6) R(7) \ 74 R(8) R(9) R(10) R(11) R(12) R(13) R(14) R(15) \ 75 R(16) R(17) R(18) R(19) R(20) R(21) R(22) R(23) \ 76 R(24) R(25) R(26) R(27) R(28) R(29) R(30) R(31) 77 78 // SVE loads and stores use "w" instead of "s" for word-sized accesses, so the 79 // mapping from the load/store variant to constants like k*RegSize is irregular. 80 #define VIXL_SVE_LOAD_STORE_VARIANT_LIST(V) \ 81 V(b, B) \ 82 V(h, H) \ 83 V(w, S) \ 84 V(d, D) 85 86 // Sign-extending loads don't have double-word variants. 87 #define VIXL_SVE_LOAD_STORE_SIGNED_VARIANT_LIST(V) \ 88 V(b, B) \ 89 V(h, H) \ 90 V(w, S) 91 92 #define INSTRUCTION_FIELDS_LIST(V_) \ 93 /* Register fields */ \ 94 V_(Rd, 4, 0, ExtractBits) /* Destination register. */ \ 95 V_(Rn, 9, 5, ExtractBits) /* First source register. */ \ 96 V_(Rm, 20, 16, ExtractBits) /* Second source register. */ \ 97 V_(RmLow16, 19, 16, ExtractBits) /* Second source register (code 0-15). */ \ 98 V_(Ra, 14, 10, ExtractBits) /* Third source register. */ \ 99 V_(Rt, 4, 0, ExtractBits) /* Load/store register. */ \ 100 V_(Rt2, 14, 10, ExtractBits) /* Load/store second register. */ \ 101 V_(Rs, 20, 16, ExtractBits) /* Exclusive access status. */ \ 102 V_(Pt, 3, 0, ExtractBits) /* Load/store register (p0-p7). */ \ 103 V_(Pd, 3, 0, ExtractBits) /* SVE destination predicate register. */ \ 104 V_(Pn, 8, 5, ExtractBits) /* SVE first source predicate register. */ \ 105 V_(Pm, 19, 16, ExtractBits) /* SVE second source predicate register.*/ \ 106 V_(PgLow8, 12, 10, ExtractBits) /* Governing predicate (p0-p7). */ \ 107 \ 108 /* Common bits */ \ 109 V_(SixtyFourBits, 31, 31, ExtractBits) \ 110 V_(FlagsUpdate, 29, 29, ExtractBits) \ 111 \ 112 /* PC relative addressing */ \ 113 V_(ImmPCRelHi, 23, 5, ExtractSignedBits) \ 114 V_(ImmPCRelLo, 30, 29, ExtractBits) \ 115 \ 116 /* Add/subtract/logical shift register */ \ 117 V_(ShiftDP, 23, 22, ExtractBits) \ 118 V_(ImmDPShift, 15, 10, ExtractBits) \ 119 \ 120 /* Add/subtract immediate */ \ 121 V_(ImmAddSub, 21, 10, ExtractBits) \ 122 V_(ImmAddSubShift, 22, 22, ExtractBits) \ 123 \ 124 /* Add/substract extend */ \ 125 V_(ImmExtendShift, 12, 10, ExtractBits) \ 126 V_(ExtendMode, 15, 13, ExtractBits) \ 127 \ 128 /* Move wide */ \ 129 V_(ImmMoveWide, 20, 5, ExtractBits) \ 130 V_(ShiftMoveWide, 22, 21, ExtractBits) \ 131 \ 132 /* Logical immediate, bitfield and extract */ \ 133 V_(BitN, 22, 22, ExtractBits) \ 134 V_(ImmRotate, 21, 16, ExtractBits) \ 135 V_(ImmSetBits, 15, 10, ExtractBits) \ 136 V_(ImmR, 21, 16, ExtractBits) \ 137 V_(ImmS, 15, 10, ExtractBits) \ 138 \ 139 /* Test and branch immediate */ \ 140 V_(ImmTestBranch, 18, 5, ExtractSignedBits) \ 141 V_(ImmTestBranchBit40, 23, 19, ExtractBits) \ 142 V_(ImmTestBranchBit5, 31, 31, ExtractBits) \ 143 \ 144 /* Conditionals */ \ 145 V_(Condition, 15, 12, ExtractBits) \ 146 V_(ConditionBranch, 3, 0, ExtractBits) \ 147 V_(Nzcv, 3, 0, ExtractBits) \ 148 V_(ImmCondCmp, 20, 16, ExtractBits) \ 149 V_(ImmCondBranch, 23, 5, ExtractSignedBits) \ 150 \ 151 /* Floating point */ \ 152 V_(FPType, 23, 22, ExtractBits) \ 153 V_(ImmFP, 20, 13, ExtractBits) \ 154 V_(FPScale, 15, 10, ExtractBits) \ 155 \ 156 /* Load Store */ \ 157 V_(ImmLS, 20, 12, ExtractSignedBits) \ 158 V_(ImmLSUnsigned, 21, 10, ExtractBits) \ 159 V_(ImmLSPair, 21, 15, ExtractSignedBits) \ 160 V_(ImmShiftLS, 12, 12, ExtractBits) \ 161 V_(LSOpc, 23, 22, ExtractBits) \ 162 V_(LSVector, 26, 26, ExtractBits) \ 163 V_(LSSize, 31, 30, ExtractBits) \ 164 V_(ImmPrefetchOperation, 4, 0, ExtractBits) \ 165 V_(PrefetchHint, 4, 3, ExtractBits) \ 166 V_(PrefetchTarget, 2, 1, ExtractBits) \ 167 V_(PrefetchStream, 0, 0, ExtractBits) \ 168 V_(ImmLSPACHi, 22, 22, ExtractSignedBits) \ 169 V_(ImmLSPACLo, 20, 12, ExtractBits) \ 170 \ 171 /* Other immediates */ \ 172 V_(ImmUncondBranch, 25, 0, ExtractSignedBits) \ 173 V_(ImmCmpBranch, 23, 5, ExtractSignedBits) \ 174 V_(ImmLLiteral, 23, 5, ExtractSignedBits) \ 175 V_(ImmException, 20, 5, ExtractBits) \ 176 V_(ImmHint, 11, 5, ExtractBits) \ 177 V_(ImmBarrierDomain, 11, 10, ExtractBits) \ 178 V_(ImmBarrierType, 9, 8, ExtractBits) \ 179 V_(ImmUdf, 15, 0, ExtractBits) \ 180 \ 181 /* System (MRS, MSR, SYS) */ \ 182 V_(ImmSystemRegister, 20, 5, ExtractBits) \ 183 V_(SysO0, 19, 19, ExtractBits) \ 184 V_(SysOp, 18, 5, ExtractBits) \ 185 V_(SysOp0, 20, 19, ExtractBits) \ 186 V_(SysOp1, 18, 16, ExtractBits) \ 187 V_(SysOp2, 7, 5, ExtractBits) \ 188 V_(CRn, 15, 12, ExtractBits) \ 189 V_(CRm, 11, 8, ExtractBits) \ 190 V_(ImmRMIFRotation, 20, 15, ExtractBits) \ 191 \ 192 /* Load-/store-exclusive */ \ 193 V_(LdStXLoad, 22, 22, ExtractBits) \ 194 V_(LdStXNotExclusive, 23, 23, ExtractBits) \ 195 V_(LdStXAcquireRelease, 15, 15, ExtractBits) \ 196 V_(LdStXSizeLog2, 31, 30, ExtractBits) \ 197 V_(LdStXPair, 21, 21, ExtractBits) \ 198 \ 199 /* NEON generic fields */ \ 200 V_(NEONQ, 30, 30, ExtractBits) \ 201 V_(NEONSize, 23, 22, ExtractBits) \ 202 V_(NEONLSSize, 11, 10, ExtractBits) \ 203 V_(NEONS, 12, 12, ExtractBits) \ 204 V_(NEONL, 21, 21, ExtractBits) \ 205 V_(NEONM, 20, 20, ExtractBits) \ 206 V_(NEONH, 11, 11, ExtractBits) \ 207 V_(ImmNEONExt, 14, 11, ExtractBits) \ 208 V_(ImmNEON5, 20, 16, ExtractBits) \ 209 V_(ImmNEON4, 14, 11, ExtractBits) \ 210 \ 211 /* NEON extra fields */ \ 212 V_(ImmRotFcadd, 12, 12, ExtractBits) \ 213 V_(ImmRotFcmlaVec, 12, 11, ExtractBits) \ 214 V_(ImmRotFcmlaSca, 14, 13, ExtractBits) \ 215 \ 216 /* NEON Modified Immediate fields */ \ 217 V_(ImmNEONabc, 18, 16, ExtractBits) \ 218 V_(ImmNEONdefgh, 9, 5, ExtractBits) \ 219 V_(NEONModImmOp, 29, 29, ExtractBits) \ 220 V_(NEONCmode, 15, 12, ExtractBits) \ 221 \ 222 /* NEON Shift Immediate fields */ \ 223 V_(ImmNEONImmhImmb, 22, 16, ExtractBits) \ 224 V_(ImmNEONImmh, 22, 19, ExtractBits) \ 225 V_(ImmNEONImmb, 18, 16, ExtractBits) \ 226 \ 227 /* SVE generic fields */ \ 228 V_(SVESize, 23, 22, ExtractBits) \ 229 V_(ImmSVEVLScale, 10, 5, ExtractSignedBits) \ 230 V_(ImmSVEIntWideSigned, 12, 5, ExtractSignedBits) \ 231 V_(ImmSVEIntWideUnsigned, 12, 5, ExtractBits) \ 232 V_(ImmSVEPredicateConstraint, 9, 5, ExtractBits) \ 233 \ 234 /* SVE Bitwise Immediate bitfield */ \ 235 V_(SVEBitN, 17, 17, ExtractBits) \ 236 V_(SVEImmRotate, 16, 11, ExtractBits) \ 237 V_(SVEImmSetBits, 10, 5, ExtractBits) \ 238 \ 239 V_(SVEImmPrefetchOperation, 3, 0, ExtractBits) \ 240 V_(SVEPrefetchHint, 3, 3, ExtractBits) 241 242 // clang-format on 243 244 #define SYSTEM_REGISTER_FIELDS_LIST(V_, M_) \ 245 /* NZCV */ \ 246 V_(Flags, 31, 28, ExtractBits) \ 247 V_(N, 31, 31, ExtractBits) \ 248 V_(Z, 30, 30, ExtractBits) \ 249 V_(C, 29, 29, ExtractBits) \ 250 V_(V, 28, 28, ExtractBits) \ 251 M_(NZCV, Flags_mask) \ 252 /* FPCR */ \ 253 V_(AHP, 26, 26, ExtractBits) \ 254 V_(DN, 25, 25, ExtractBits) \ 255 V_(FZ, 24, 24, ExtractBits) \ 256 V_(RMode, 23, 22, ExtractBits) \ 257 M_(FPCR, AHP_mask | DN_mask | FZ_mask | RMode_mask) 258 259 // Fields offsets. 260 #define DECLARE_FIELDS_OFFSETS(Name, HighBit, LowBit, X) \ 261 const int Name##_offset = LowBit; \ 262 const int Name##_width = HighBit - LowBit + 1; \ 263 const uint32_t Name##_mask = ((1 << Name##_width) - 1) << LowBit; 264 #define NOTHING(A, B) 265 INSTRUCTION_FIELDS_LIST(DECLARE_FIELDS_OFFSETS) 266 SYSTEM_REGISTER_FIELDS_LIST(DECLARE_FIELDS_OFFSETS, NOTHING) 267 #undef NOTHING 268 #undef DECLARE_FIELDS_BITS 269 270 // ImmPCRel is a compound field (not present in INSTRUCTION_FIELDS_LIST), formed 271 // from ImmPCRelLo and ImmPCRelHi. 272 const int ImmPCRel_mask = ImmPCRelLo_mask | ImmPCRelHi_mask; 273 274 // Disable `clang-format` for the `enum`s below. We care about the manual 275 // formatting that `clang-format` would destroy. 276 // clang-format off 277 278 // Condition codes. 279 enum Condition { 280 eq = 0, // Z set Equal. 281 ne = 1, // Z clear Not equal. 282 cs = 2, // C set Carry set. 283 cc = 3, // C clear Carry clear. 284 mi = 4, // N set Negative. 285 pl = 5, // N clear Positive or zero. 286 vs = 6, // V set Overflow. 287 vc = 7, // V clear No overflow. 288 hi = 8, // C set, Z clear Unsigned higher. 289 ls = 9, // C clear or Z set Unsigned lower or same. 290 ge = 10, // N == V Greater or equal. 291 lt = 11, // N != V Less than. 292 gt = 12, // Z clear, N == V Greater than. 293 le = 13, // Z set or N != V Less then or equal 294 al = 14, // Always. 295 nv = 15, // Behaves as always/al. 296 297 // Aliases. 298 hs = cs, // C set Unsigned higher or same. 299 lo = cc, // C clear Unsigned lower. 300 301 // Floating-point additional condition code. 302 uo, // Unordered comparison. 303 304 // SVE predicate condition aliases. 305 sve_none = eq, // No active elements were true. 306 sve_any = ne, // An active element was true. 307 sve_nlast = cs, // The last element was not true. 308 sve_last = cc, // The last element was true. 309 sve_first = mi, // The first element was true. 310 sve_nfrst = pl, // The first element was not true. 311 sve_pmore = hi, // An active element was true but not the last element. 312 sve_plast = ls, // The last active element was true or no active elements were true. 313 sve_tcont = ge, // CTERM termination condition not deleted. 314 sve_tstop = lt, // CTERM termination condition deleted. 315 316 // Mozilla expanded aliases. 317 Equal = 0, Zero = 0, 318 NotEqual = 1, NonZero = 1, 319 AboveOrEqual = 2, CarrySet = 2, 320 Below = 3, CarryClear = 3, 321 Signed = 4, 322 NotSigned = 5, 323 Overflow = 6, 324 NoOverflow = 7, 325 Above = 8, 326 BelowOrEqual = 9, 327 GreaterThanOrEqual_ = 10, 328 LessThan_ = 11, 329 GreaterThan_ = 12, 330 LessThanOrEqual_ = 13, 331 Always = 14, 332 Never = 15 333 }; 334 335 inline Condition InvertCondition(Condition cond) { 336 // Conditions al and nv behave identically, as "always true". They can't be 337 // inverted, because there is no "always false" condition. 338 VIXL_ASSERT((cond != al) && (cond != nv)); 339 return static_cast<Condition>(cond ^ 1); 340 } 341 342 enum FPTrapFlags { 343 EnableTrap = 1, 344 DisableTrap = 0 345 }; 346 347 enum FlagsUpdate { 348 SetFlags = 1, 349 LeaveFlags = 0 350 }; 351 352 enum StatusFlags { 353 NoFlag = 0, 354 355 // Derive the flag combinations from the system register bit descriptions. 356 NFlag = N_mask, 357 ZFlag = Z_mask, 358 CFlag = C_mask, 359 VFlag = V_mask, 360 NZFlag = NFlag | ZFlag, 361 NCFlag = NFlag | CFlag, 362 NVFlag = NFlag | VFlag, 363 ZCFlag = ZFlag | CFlag, 364 ZVFlag = ZFlag | VFlag, 365 CVFlag = CFlag | VFlag, 366 NZCFlag = NFlag | ZFlag | CFlag, 367 NZVFlag = NFlag | ZFlag | VFlag, 368 NCVFlag = NFlag | CFlag | VFlag, 369 ZCVFlag = ZFlag | CFlag | VFlag, 370 NZCVFlag = NFlag | ZFlag | CFlag | VFlag, 371 372 // Floating-point comparison results. 373 FPEqualFlag = ZCFlag, 374 FPLessThanFlag = NFlag, 375 FPGreaterThanFlag = CFlag, 376 FPUnorderedFlag = CVFlag, 377 378 // SVE condition flags. 379 SVEFirstFlag = NFlag, 380 SVENoneFlag = ZFlag, 381 SVENotLastFlag = CFlag 382 }; 383 384 // Mozilla change: Use sized enum to allow better packing for Shift uses. 385 enum Shift : int8_t { 386 NO_SHIFT = -1, 387 LSL = 0x0, 388 LSR = 0x1, 389 ASR = 0x2, 390 ROR = 0x3, 391 MSL = 0x4 392 }; 393 394 // Mozilla change: Use sized enum to allow better packing for Extend uses. 395 enum Extend : int8_t { 396 NO_EXTEND = -1, 397 UXTB = 0, 398 UXTH = 1, 399 UXTW = 2, 400 UXTX = 3, 401 SXTB = 4, 402 SXTH = 5, 403 SXTW = 6, 404 SXTX = 7 405 }; 406 407 enum SVEOffsetModifier { 408 NO_SVE_OFFSET_MODIFIER, 409 // Multiply (each element of) the offset by either the vector or predicate 410 // length, according to the context. 411 SVE_MUL_VL, 412 // Shift or extend modifiers (as in `Shift` or `Extend`). 413 SVE_LSL, 414 SVE_UXTW, 415 SVE_SXTW 416 }; 417 418 enum SystemHint { 419 NOP = 0, 420 YIELD = 1, 421 WFE = 2, 422 WFI = 3, 423 SEV = 4, 424 SEVL = 5, 425 ESB = 16, 426 CSDB = 20, 427 BTI = 32, 428 BTI_c = 34, 429 BTI_j = 36, 430 BTI_jc = 38, 431 CHKFEAT = 40 432 }; 433 434 enum BranchTargetIdentifier { 435 EmitBTI_none = NOP, 436 EmitBTI = BTI, 437 EmitBTI_c = BTI_c, 438 EmitBTI_j = BTI_j, 439 EmitBTI_jc = BTI_jc, 440 441 // These correspond to the values of the CRm:op2 fields in the equivalent HINT 442 // instruction. 443 EmitPACIASP = 25, 444 EmitPACIBSP = 27 445 }; 446 447 enum BarrierDomain { 448 OuterShareable = 0, 449 NonShareable = 1, 450 InnerShareable = 2, 451 FullSystem = 3 452 }; 453 454 enum BarrierType { 455 BarrierOther = 0, 456 BarrierReads = 1, 457 BarrierWrites = 2, 458 BarrierAll = 3 459 }; 460 461 enum PrefetchOperation { 462 PLDL1KEEP = 0x00, 463 PLDL1STRM = 0x01, 464 PLDL2KEEP = 0x02, 465 PLDL2STRM = 0x03, 466 PLDL3KEEP = 0x04, 467 PLDL3STRM = 0x05, 468 469 PrfUnallocated06 = 0x06, 470 PrfUnallocated07 = 0x07, 471 472 PLIL1KEEP = 0x08, 473 PLIL1STRM = 0x09, 474 PLIL2KEEP = 0x0a, 475 PLIL2STRM = 0x0b, 476 PLIL3KEEP = 0x0c, 477 PLIL3STRM = 0x0d, 478 479 PrfUnallocated0e = 0x0e, 480 PrfUnallocated0f = 0x0f, 481 482 PSTL1KEEP = 0x10, 483 PSTL1STRM = 0x11, 484 PSTL2KEEP = 0x12, 485 PSTL2STRM = 0x13, 486 PSTL3KEEP = 0x14, 487 PSTL3STRM = 0x15, 488 489 PrfUnallocated16 = 0x16, 490 PrfUnallocated17 = 0x17, 491 PrfUnallocated18 = 0x18, 492 PrfUnallocated19 = 0x19, 493 PrfUnallocated1a = 0x1a, 494 PrfUnallocated1b = 0x1b, 495 PrfUnallocated1c = 0x1c, 496 PrfUnallocated1d = 0x1d, 497 PrfUnallocated1e = 0x1e, 498 PrfUnallocated1f = 0x1f, 499 }; 500 501 constexpr bool IsNamedPrefetchOperation(int op) { 502 return ((op >= PLDL1KEEP) && (op <= PLDL3STRM)) || 503 ((op >= PLIL1KEEP) && (op <= PLIL3STRM)) || 504 ((op >= PSTL1KEEP) && (op <= PSTL3STRM)); 505 } 506 507 enum BType { 508 // Set when executing any instruction on a guarded page, except those cases 509 // listed below. 510 DefaultBType = 0, 511 512 // Set when an indirect branch is taken from an unguarded page to a guarded 513 // page, or from a guarded page to ip0 or ip1 (x16 or x17), eg "br ip0". 514 BranchFromUnguardedOrToIP = 1, 515 516 // Set when an indirect branch and link (call) is taken, eg. "blr x0". 517 BranchAndLink = 2, 518 519 // Set when an indirect branch is taken from a guarded page to a register 520 // that is not ip0 or ip1 (x16 or x17), eg, "br x0". 521 BranchFromGuardedNotToIP = 3 522 }; 523 524 template<int op0, int op1, int crn, int crm, int op2> 525 class SystemRegisterEncoder { 526 public: 527 static const uint32_t value = 528 ((op0 << SysO0_offset) | 529 (op1 << SysOp1_offset) | 530 (crn << CRn_offset) | 531 (crm << CRm_offset) | 532 (op2 << SysOp2_offset)) >> ImmSystemRegister_offset; 533 }; 534 535 // System/special register names. 536 // This information is not encoded as one field but as the concatenation of 537 // multiple fields (Op0, Op1, Crn, Crm, Op2). 538 enum SystemRegister { 539 NZCV = SystemRegisterEncoder<3, 3, 4, 2, 0>::value, 540 FPCR = SystemRegisterEncoder<3, 3, 4, 4, 0>::value, 541 RNDR = SystemRegisterEncoder<3, 3, 2, 4, 0>::value, // Random number. 542 RNDRRS = SystemRegisterEncoder<3, 3, 2, 4, 1>::value, // Reseeded random number. 543 DCZID_EL0 = SystemRegisterEncoder<3, 3, 0, 0, 7>::value 544 }; 545 546 template<int op1, int crn, int crm, int op2> 547 class CacheOpEncoder { 548 public: 549 static const uint32_t value = 550 ((op1 << SysOp1_offset) | 551 (crn << CRn_offset) | 552 (crm << CRm_offset) | 553 (op2 << SysOp2_offset)) >> SysOp_offset; 554 }; 555 556 enum InstructionCacheOp : uint32_t { 557 IVAU = CacheOpEncoder<3, 7, 5, 1>::value 558 }; 559 560 enum DataCacheOp : uint32_t { 561 CVAC = CacheOpEncoder<3, 7, 10, 1>::value, 562 CVAU = CacheOpEncoder<3, 7, 11, 1>::value, 563 CVAP = CacheOpEncoder<3, 7, 12, 1>::value, 564 CVADP = CacheOpEncoder<3, 7, 13, 1>::value, 565 CIVAC = CacheOpEncoder<3, 7, 14, 1>::value, 566 ZVA = CacheOpEncoder<3, 7, 4, 1>::value, 567 GVA = CacheOpEncoder<3, 7, 4, 3>::value, 568 GZVA = CacheOpEncoder<3, 7, 4, 4>::value, 569 CGVAC = CacheOpEncoder<3, 7, 10, 3>::value, 570 CGDVAC = CacheOpEncoder<3, 7, 10, 5>::value, 571 CGVAP = CacheOpEncoder<3, 7, 12, 3>::value, 572 CGDVAP = CacheOpEncoder<3, 7, 12, 5>::value, 573 CIGVAC = CacheOpEncoder<3, 7, 14, 3>::value, 574 CIGDVAC = CacheOpEncoder<3, 7, 14, 5>::value 575 }; 576 577 enum GCSOp { 578 GCSPUSHM = CacheOpEncoder<3, 7, 7, 0>::value, 579 GCSPOPM = CacheOpEncoder<3, 7, 7, 1>::value, 580 GCSSS1 = CacheOpEncoder<3, 7, 7, 2>::value, 581 GCSSS2 = CacheOpEncoder<3, 7, 7, 3>::value 582 }; 583 584 // Some SVE instructions support a predicate constraint pattern. This is 585 // interpreted as a VL-dependent value, and is typically used to initialise 586 // predicates, or to otherwise limit the number of processed elements. 587 enum SVEPredicateConstraint { 588 // Select 2^N elements, for the largest possible N. 589 SVE_POW2 = 0x0, 590 // Each VL<N> selects exactly N elements if possible, or zero if N is greater 591 // than the number of elements. Note that the encoding values for VL<N> are 592 // not linearly related to N. 593 SVE_VL1 = 0x1, 594 SVE_VL2 = 0x2, 595 SVE_VL3 = 0x3, 596 SVE_VL4 = 0x4, 597 SVE_VL5 = 0x5, 598 SVE_VL6 = 0x6, 599 SVE_VL7 = 0x7, 600 SVE_VL8 = 0x8, 601 SVE_VL16 = 0x9, 602 SVE_VL32 = 0xa, 603 SVE_VL64 = 0xb, 604 SVE_VL128 = 0xc, 605 SVE_VL256 = 0xd, 606 // Each MUL<N> selects the largest multiple of N elements that the vector 607 // length supports. Note that for D-sized lanes, this can be zero. 608 SVE_MUL4 = 0x1d, 609 SVE_MUL3 = 0x1e, 610 // Select all elements. 611 SVE_ALL = 0x1f 612 }; 613 614 // Instruction enumerations. 615 // 616 // These are the masks that define a class of instructions, and the list of 617 // instructions within each class. Each enumeration has a Fixed, FMask and 618 // Mask value. 619 // 620 // Fixed: The fixed bits in this instruction class. 621 // FMask: The mask used to extract the fixed bits in the class. 622 // Mask: The mask used to identify the instructions within a class. 623 // 624 // The enumerations can be used like this: 625 // 626 // VIXL_ASSERT(instr->Mask(PCRelAddressingFMask) == PCRelAddressingFixed); 627 // switch(instr->Mask(PCRelAddressingMask)) { 628 // case ADR: Format("adr 'Xd, 'AddrPCRelByte"); break; 629 // case ADRP: Format("adrp 'Xd, 'AddrPCRelPage"); break; 630 // default: printf("Unknown instruction\n"); 631 // } 632 633 634 // Generic fields. 635 using GenericInstrField = uint32_t; 636 constexpr GenericInstrField 637 SixtyFourBits = 0x80000000, 638 ThirtyTwoBits = 0x00000000, 639 640 FPTypeMask = 0x00C00000, 641 FP16 = 0x00C00000, 642 FP32 = 0x00000000, 643 FP64 = 0x00400000 644 ; 645 646 using NEONFormatField = uint32_t; 647 constexpr NEONFormatField 648 NEONFormatFieldMask = 0x40C00000, 649 NEON_Q = 0x40000000, 650 NEON_8B = 0x00000000, 651 NEON_16B = NEON_8B | NEON_Q, 652 NEON_4H = 0x00400000, 653 NEON_8H = NEON_4H | NEON_Q, 654 NEON_2S = 0x00800000, 655 NEON_4S = NEON_2S | NEON_Q, 656 NEON_1D = 0x00C00000, 657 NEON_2D = 0x00C00000 | NEON_Q 658 ; 659 660 enum NEONFPFormatField : uint32_t { 661 NEONFPFormatFieldMask = 0x40400000, 662 NEON_FP_4H = FP16, 663 NEON_FP_2S = FP32, 664 NEON_FP_8H = FP16 | NEON_Q, 665 NEON_FP_4S = FP32 | NEON_Q, 666 NEON_FP_2D = FP64 | NEON_Q 667 }; 668 669 enum NEONLSFormatField : uint32_t { 670 NEONLSFormatFieldMask = 0x40000C00, 671 LS_NEON_8B = 0x00000000, 672 LS_NEON_16B = LS_NEON_8B | NEON_Q, 673 LS_NEON_4H = 0x00000400, 674 LS_NEON_8H = LS_NEON_4H | NEON_Q, 675 LS_NEON_2S = 0x00000800, 676 LS_NEON_4S = LS_NEON_2S | NEON_Q, 677 LS_NEON_1D = 0x00000C00, 678 LS_NEON_2D = LS_NEON_1D | NEON_Q 679 }; 680 681 enum NEONScalarFormatField : uint32_t { 682 NEONScalarFormatFieldMask = 0x00C00000, 683 NEONScalar = 0x10000000, 684 NEON_B = 0x00000000, 685 NEON_H = 0x00400000, 686 NEON_S = 0x00800000, 687 NEON_D = 0x00C00000 688 }; 689 690 enum SVESizeField { 691 SVESizeFieldMask = 0x00C00000, 692 SVE_B = 0x00000000, 693 SVE_H = 0x00400000, 694 SVE_S = 0x00800000, 695 SVE_D = 0x00C00000 696 }; 697 698 // PC relative addressing. 699 enum PCRelAddressingOp : uint32_t { 700 PCRelAddressingFixed = 0x10000000, 701 PCRelAddressingFMask = 0x1F000000, 702 PCRelAddressingMask = 0x9F000000, 703 ADR = PCRelAddressingFixed | 0x00000000, 704 ADRP = PCRelAddressingFixed | 0x80000000 705 }; 706 707 // Add/sub (immediate, shifted and extended.) 708 const int kSFOffset = 31; 709 enum AddSubOp : uint32_t { 710 AddSubOpMask = 0x60000000, 711 AddSubSetFlagsBit = 0x20000000, 712 ADD = 0x00000000, 713 ADDS = ADD | AddSubSetFlagsBit, 714 SUB = 0x40000000, 715 SUBS = SUB | AddSubSetFlagsBit 716 }; 717 718 #define ADD_SUB_OP_LIST(V) \ 719 V(ADD), \ 720 V(ADDS), \ 721 V(SUB), \ 722 V(SUBS) 723 724 enum AddSubImmediateOp : uint32_t { 725 AddSubImmediateFixed = 0x11000000, 726 AddSubImmediateFMask = 0x1F800000, 727 AddSubImmediateMask = 0xFF800000, 728 #define ADD_SUB_IMMEDIATE(A) \ 729 A##_w_imm = AddSubImmediateFixed | A, \ 730 A##_x_imm = AddSubImmediateFixed | A | SixtyFourBits 731 ADD_SUB_OP_LIST(ADD_SUB_IMMEDIATE) 732 #undef ADD_SUB_IMMEDIATE 733 }; 734 735 enum AddSubShiftedOp : uint32_t { 736 AddSubShiftedFixed = 0x0B000000, 737 AddSubShiftedFMask = 0x1F200000, 738 AddSubShiftedMask = 0xFF200000, 739 #define ADD_SUB_SHIFTED(A) \ 740 A##_w_shift = AddSubShiftedFixed | A, \ 741 A##_x_shift = AddSubShiftedFixed | A | SixtyFourBits 742 ADD_SUB_OP_LIST(ADD_SUB_SHIFTED) 743 #undef ADD_SUB_SHIFTED 744 }; 745 746 enum AddSubExtendedOp : uint32_t { 747 AddSubExtendedFixed = 0x0B200000, 748 AddSubExtendedFMask = 0x1F200000, 749 AddSubExtendedMask = 0xFFE00000, 750 #define ADD_SUB_EXTENDED(A) \ 751 A##_w_ext = AddSubExtendedFixed | A, \ 752 A##_x_ext = AddSubExtendedFixed | A | SixtyFourBits 753 ADD_SUB_OP_LIST(ADD_SUB_EXTENDED) 754 #undef ADD_SUB_EXTENDED 755 }; 756 757 // Add/sub with carry. 758 enum AddSubWithCarryOp : uint32_t { 759 AddSubWithCarryFixed = 0x1A000000, 760 AddSubWithCarryFMask = 0x1FE00000, 761 AddSubWithCarryMask = 0xFFE0FC00, 762 ADC_w = AddSubWithCarryFixed | ADD, 763 ADC_x = AddSubWithCarryFixed | ADD | SixtyFourBits, 764 ADC = ADC_w, 765 ADCS_w = AddSubWithCarryFixed | ADDS, 766 ADCS_x = AddSubWithCarryFixed | ADDS | SixtyFourBits, 767 SBC_w = AddSubWithCarryFixed | SUB, 768 SBC_x = AddSubWithCarryFixed | SUB | SixtyFourBits, 769 SBC = SBC_w, 770 SBCS_w = AddSubWithCarryFixed | SUBS, 771 SBCS_x = AddSubWithCarryFixed | SUBS | SixtyFourBits 772 }; 773 774 // Rotate right into flags. 775 enum RotateRightIntoFlagsOp : uint32_t { 776 RotateRightIntoFlagsFixed = 0x1A000400, 777 RotateRightIntoFlagsFMask = 0x1FE07C00, 778 RotateRightIntoFlagsMask = 0xFFE07C10, 779 RMIF = RotateRightIntoFlagsFixed | 0xA0000000 780 }; 781 782 // Evaluate into flags. 783 enum EvaluateIntoFlagsOp : uint32_t { 784 EvaluateIntoFlagsFixed = 0x1A000800, 785 EvaluateIntoFlagsFMask = 0x1FE03C00, 786 EvaluateIntoFlagsMask = 0xFFE07C1F, 787 SETF8 = EvaluateIntoFlagsFixed | 0x2000000D, 788 SETF16 = EvaluateIntoFlagsFixed | 0x2000400D 789 }; 790 791 792 // Logical (immediate and shifted register). 793 enum LogicalOp : uint32_t { 794 LogicalOpMask = 0x60200000, 795 NOT = 0x00200000, 796 AND = 0x00000000, 797 BIC = AND | NOT, 798 ORR = 0x20000000, 799 ORN = ORR | NOT, 800 EOR = 0x40000000, 801 EON = EOR | NOT, 802 ANDS = 0x60000000, 803 BICS = ANDS | NOT 804 }; 805 806 // Logical immediate. 807 enum LogicalImmediateOp : uint32_t { 808 LogicalImmediateFixed = 0x12000000, 809 LogicalImmediateFMask = 0x1F800000, 810 LogicalImmediateMask = 0xFF800000, 811 AND_w_imm = LogicalImmediateFixed | AND, 812 AND_x_imm = LogicalImmediateFixed | AND | SixtyFourBits, 813 ORR_w_imm = LogicalImmediateFixed | ORR, 814 ORR_x_imm = LogicalImmediateFixed | ORR | SixtyFourBits, 815 EOR_w_imm = LogicalImmediateFixed | EOR, 816 EOR_x_imm = LogicalImmediateFixed | EOR | SixtyFourBits, 817 ANDS_w_imm = LogicalImmediateFixed | ANDS, 818 ANDS_x_imm = LogicalImmediateFixed | ANDS | SixtyFourBits 819 }; 820 821 // Logical shifted register. 822 enum LogicalShiftedOp : uint32_t { 823 LogicalShiftedFixed = 0x0A000000, 824 LogicalShiftedFMask = 0x1F000000, 825 LogicalShiftedMask = 0xFF200000, 826 AND_w = LogicalShiftedFixed | AND, 827 AND_x = LogicalShiftedFixed | AND | SixtyFourBits, 828 AND_shift = AND_w, 829 BIC_w = LogicalShiftedFixed | BIC, 830 BIC_x = LogicalShiftedFixed | BIC | SixtyFourBits, 831 BIC_shift = BIC_w, 832 ORR_w = LogicalShiftedFixed | ORR, 833 ORR_x = LogicalShiftedFixed | ORR | SixtyFourBits, 834 ORR_shift = ORR_w, 835 ORN_w = LogicalShiftedFixed | ORN, 836 ORN_x = LogicalShiftedFixed | ORN | SixtyFourBits, 837 ORN_shift = ORN_w, 838 EOR_w = LogicalShiftedFixed | EOR, 839 EOR_x = LogicalShiftedFixed | EOR | SixtyFourBits, 840 EOR_shift = EOR_w, 841 EON_w = LogicalShiftedFixed | EON, 842 EON_x = LogicalShiftedFixed | EON | SixtyFourBits, 843 EON_shift = EON_w, 844 ANDS_w = LogicalShiftedFixed | ANDS, 845 ANDS_x = LogicalShiftedFixed | ANDS | SixtyFourBits, 846 ANDS_shift = ANDS_w, 847 BICS_w = LogicalShiftedFixed | BICS, 848 BICS_x = LogicalShiftedFixed | BICS | SixtyFourBits, 849 BICS_shift = BICS_w 850 }; 851 852 // Move wide immediate. 853 enum MoveWideImmediateOp : uint32_t { 854 MoveWideImmediateFixed = 0x12800000, 855 MoveWideImmediateFMask = 0x1F800000, 856 MoveWideImmediateMask = 0xFF800000, 857 MOVN = 0x00000000, 858 MOVZ = 0x40000000, 859 MOVK = 0x60000000, 860 MOVN_w = MoveWideImmediateFixed | MOVN, 861 MOVN_x = MoveWideImmediateFixed | MOVN | SixtyFourBits, 862 MOVZ_w = MoveWideImmediateFixed | MOVZ, 863 MOVZ_x = MoveWideImmediateFixed | MOVZ | SixtyFourBits, 864 MOVK_w = MoveWideImmediateFixed | MOVK, 865 MOVK_x = MoveWideImmediateFixed | MOVK | SixtyFourBits 866 }; 867 868 // Bitfield. 869 const int kBitfieldNOffset = 22; 870 enum BitfieldOp : uint32_t { 871 BitfieldFixed = 0x13000000, 872 BitfieldFMask = 0x1F800000, 873 BitfieldMask = 0xFF800000, 874 SBFM_w = BitfieldFixed | 0x00000000, 875 SBFM_x = BitfieldFixed | 0x80000000, 876 SBFM = SBFM_w, 877 BFM_w = BitfieldFixed | 0x20000000, 878 BFM_x = BitfieldFixed | 0xA0000000, 879 BFM = BFM_w, 880 UBFM_w = BitfieldFixed | 0x40000000, 881 UBFM_x = BitfieldFixed | 0xC0000000, 882 UBFM = UBFM_w 883 // Bitfield N field. 884 }; 885 886 // Extract. 887 enum ExtractOp : uint32_t { 888 ExtractFixed = 0x13800000, 889 ExtractFMask = 0x1F800000, 890 ExtractMask = 0xFFA00000, 891 EXTR_w = ExtractFixed | 0x00000000, 892 EXTR_x = ExtractFixed | 0x80000000, 893 EXTR = EXTR_w 894 }; 895 896 // Unconditional branch. 897 enum UnconditionalBranchOp : uint32_t { 898 UnconditionalBranchFixed = 0x14000000, 899 UnconditionalBranchFMask = 0x7C000000, 900 UnconditionalBranchMask = 0xFC000000, 901 B = UnconditionalBranchFixed | 0x00000000, 902 BL = UnconditionalBranchFixed | 0x80000000 903 }; 904 905 // Unconditional branch to register. 906 enum UnconditionalBranchToRegisterOp : uint32_t { 907 UnconditionalBranchToRegisterFixed = 0xD6000000, 908 UnconditionalBranchToRegisterFMask = 0xFE000000, 909 UnconditionalBranchToRegisterMask = 0xFFFFFC00, 910 BR = UnconditionalBranchToRegisterFixed | 0x001F0000, 911 BLR = UnconditionalBranchToRegisterFixed | 0x003F0000, 912 RET = UnconditionalBranchToRegisterFixed | 0x005F0000, 913 914 BRAAZ = UnconditionalBranchToRegisterFixed | 0x001F0800, 915 BRABZ = UnconditionalBranchToRegisterFixed | 0x001F0C00, 916 BLRAAZ = UnconditionalBranchToRegisterFixed | 0x003F0800, 917 BLRABZ = UnconditionalBranchToRegisterFixed | 0x003F0C00, 918 RETAA = UnconditionalBranchToRegisterFixed | 0x005F0800, 919 RETAB = UnconditionalBranchToRegisterFixed | 0x005F0C00, 920 BRAA = UnconditionalBranchToRegisterFixed | 0x011F0800, 921 BRAB = UnconditionalBranchToRegisterFixed | 0x011F0C00, 922 BLRAA = UnconditionalBranchToRegisterFixed | 0x013F0800, 923 BLRAB = UnconditionalBranchToRegisterFixed | 0x013F0C00 924 }; 925 926 // Compare and branch. 927 enum CompareBranchOp : uint32_t { 928 CompareBranchFixed = 0x34000000, 929 CompareBranchFMask = 0x7E000000, 930 CompareBranchMask = 0xFF000000, 931 CBZ_w = CompareBranchFixed | 0x00000000, 932 CBZ_x = CompareBranchFixed | 0x80000000, 933 CBZ = CBZ_w, 934 CBNZ_w = CompareBranchFixed | 0x01000000, 935 CBNZ_x = CompareBranchFixed | 0x81000000, 936 CBNZ = CBNZ_w 937 }; 938 939 // Test and branch. 940 enum TestBranchOp : uint32_t { 941 TestBranchFixed = 0x36000000, 942 TestBranchFMask = 0x7E000000, 943 TestBranchMask = 0x7F000000, 944 TBZ = TestBranchFixed | 0x00000000, 945 TBNZ = TestBranchFixed | 0x01000000 946 }; 947 948 // Conditional branch. 949 enum ConditionalBranchOp : uint32_t { 950 ConditionalBranchFixed = 0x54000000, 951 ConditionalBranchFMask = 0xFE000000, 952 ConditionalBranchMask = 0xFF000010, 953 B_cond = ConditionalBranchFixed | 0x00000000 954 }; 955 956 // System. 957 // System instruction encoding is complicated because some instructions use op 958 // and CR fields to encode parameters. To handle this cleanly, the system 959 // instructions are split into more than one enum. 960 961 enum SystemOp : uint32_t { 962 SystemFixed = 0xD5000000, 963 SystemFMask = 0xFFC00000 964 }; 965 966 enum SystemSysRegOp : uint32_t { 967 SystemSysRegFixed = 0xD5100000, 968 SystemSysRegFMask = 0xFFD00000, 969 SystemSysRegMask = 0xFFF00000, 970 MRS = SystemSysRegFixed | 0x00200000, 971 MSR = SystemSysRegFixed | 0x00000000 972 }; 973 974 enum SystemPStateOp : uint32_t { 975 SystemPStateFixed = 0xD5004000, 976 SystemPStateFMask = 0xFFF8F000, 977 SystemPStateMask = 0xFFFFF0FF, 978 CFINV = SystemPStateFixed | 0x0000001F, 979 XAFLAG = SystemPStateFixed | 0x0000003F, 980 AXFLAG = SystemPStateFixed | 0x0000005F 981 }; 982 983 enum SystemHintOp : uint32_t { 984 SystemHintFixed = 0xD503201F, 985 SystemHintFMask = 0xFFFFF01F, 986 SystemHintMask = 0xFFFFF01F, 987 HINT = SystemHintFixed | 0x00000000 988 }; 989 990 enum SystemSysOp : uint32_t { 991 SystemSysFixed = 0xD5080000, 992 SystemSysFMask = 0xFFF80000, 993 SystemSysMask = 0xFFF80000, 994 SYS = SystemSysFixed | 0x00000000, 995 SYSL = SystemSysFixed | 0x00200000 996 }; 997 998 // Exception. 999 enum ExceptionOp : uint32_t { 1000 ExceptionFixed = 0xD4000000, 1001 ExceptionFMask = 0xFF000000, 1002 ExceptionMask = 0xFFE0001F, 1003 HLT = ExceptionFixed | 0x00400000, 1004 BRK = ExceptionFixed | 0x00200000, 1005 SVC = ExceptionFixed | 0x00000001, 1006 HVC = ExceptionFixed | 0x00000002, 1007 SMC = ExceptionFixed | 0x00000003, 1008 DCPS1 = ExceptionFixed | 0x00A00001, 1009 DCPS2 = ExceptionFixed | 0x00A00002, 1010 DCPS3 = ExceptionFixed | 0x00A00003, 1011 1012 // Mozilla change: 1013 // Add pseudo-instruction for Wasm traps. 1014 DCPS0 = ExceptionFixed | 0x00A00000, 1015 }; 1016 1017 enum MemBarrierOp : uint32_t { 1018 MemBarrierFixed = 0xD503309F, 1019 MemBarrierFMask = 0xFFFFF09F, 1020 MemBarrierMask = 0xFFFFF0FF, 1021 DSB = MemBarrierFixed | 0x00000000, 1022 DMB = MemBarrierFixed | 0x00000020, 1023 ISB = MemBarrierFixed | 0x00000040 1024 }; 1025 1026 enum SystemExclusiveMonitorOp : uint32_t { 1027 SystemExclusiveMonitorFixed = 0xD503305F, 1028 SystemExclusiveMonitorFMask = 0xFFFFF0FF, 1029 SystemExclusiveMonitorMask = 0xFFFFF0FF, 1030 CLREX = SystemExclusiveMonitorFixed 1031 }; 1032 1033 enum SystemPAuthOp : uint32_t { 1034 SystemPAuthFixed = 0xD503211F, 1035 SystemPAuthFMask = 0xFFFFFD1F, 1036 SystemPAuthMask = 0xFFFFFFFF, 1037 PACIA1716 = SystemPAuthFixed | 0x00000100, 1038 PACIB1716 = SystemPAuthFixed | 0x00000140, 1039 AUTIA1716 = SystemPAuthFixed | 0x00000180, 1040 AUTIB1716 = SystemPAuthFixed | 0x000001C0, 1041 PACIAZ = SystemPAuthFixed | 0x00000300, 1042 PACIASP = SystemPAuthFixed | 0x00000320, 1043 PACIBZ = SystemPAuthFixed | 0x00000340, 1044 PACIBSP = SystemPAuthFixed | 0x00000360, 1045 AUTIAZ = SystemPAuthFixed | 0x00000380, 1046 AUTIASP = SystemPAuthFixed | 0x000003A0, 1047 AUTIBZ = SystemPAuthFixed | 0x000003C0, 1048 AUTIBSP = SystemPAuthFixed | 0x000003E0, 1049 1050 // XPACLRI has the same fixed mask as System Hints and needs to be handled 1051 // differently. 1052 XPACLRI = 0xD50320FF 1053 }; 1054 1055 // Any load or store. 1056 enum LoadStoreAnyOp : uint32_t { 1057 LoadStoreAnyFMask = 0x0a000000, 1058 LoadStoreAnyFixed = 0x08000000 1059 }; 1060 1061 // Any load pair or store pair. 1062 enum LoadStorePairAnyOp : uint32_t { 1063 LoadStorePairAnyFMask = 0x3a000000, 1064 LoadStorePairAnyFixed = 0x28000000 1065 }; 1066 1067 #define LOAD_STORE_PAIR_OP_LIST(V) \ 1068 V(STP, w, 0x00000000), \ 1069 V(LDP, w, 0x00400000), \ 1070 V(LDPSW, x, 0x40400000), \ 1071 V(STP, x, 0x80000000), \ 1072 V(LDP, x, 0x80400000), \ 1073 V(STP, s, 0x04000000), \ 1074 V(LDP, s, 0x04400000), \ 1075 V(STP, d, 0x44000000), \ 1076 V(LDP, d, 0x44400000), \ 1077 V(STP, q, 0x84000000), \ 1078 V(LDP, q, 0x84400000) 1079 1080 // Load/store pair (post, pre and offset.) 1081 enum LoadStorePairOp : uint32_t { 1082 LoadStorePairMask = 0xC4400000, 1083 LoadStorePairLBit = 1 << 22, 1084 #define LOAD_STORE_PAIR(A, B, C) \ 1085 A##_##B = C 1086 LOAD_STORE_PAIR_OP_LIST(LOAD_STORE_PAIR) 1087 #undef LOAD_STORE_PAIR 1088 }; 1089 1090 enum LoadStorePairPostIndexOp : uint32_t { 1091 LoadStorePairPostIndexFixed = 0x28800000, 1092 LoadStorePairPostIndexFMask = 0x3B800000, 1093 LoadStorePairPostIndexMask = 0xFFC00000, 1094 #define LOAD_STORE_PAIR_POST_INDEX(A, B, C) \ 1095 A##_##B##_post = LoadStorePairPostIndexFixed | A##_##B 1096 LOAD_STORE_PAIR_OP_LIST(LOAD_STORE_PAIR_POST_INDEX) 1097 #undef LOAD_STORE_PAIR_POST_INDEX 1098 }; 1099 1100 enum LoadStorePairPreIndexOp : uint32_t { 1101 LoadStorePairPreIndexFixed = 0x29800000, 1102 LoadStorePairPreIndexFMask = 0x3B800000, 1103 LoadStorePairPreIndexMask = 0xFFC00000, 1104 #define LOAD_STORE_PAIR_PRE_INDEX(A, B, C) \ 1105 A##_##B##_pre = LoadStorePairPreIndexFixed | A##_##B 1106 LOAD_STORE_PAIR_OP_LIST(LOAD_STORE_PAIR_PRE_INDEX) 1107 #undef LOAD_STORE_PAIR_PRE_INDEX 1108 }; 1109 1110 enum LoadStorePairOffsetOp : uint32_t { 1111 LoadStorePairOffsetFixed = 0x29000000, 1112 LoadStorePairOffsetFMask = 0x3B800000, 1113 LoadStorePairOffsetMask = 0xFFC00000, 1114 #define LOAD_STORE_PAIR_OFFSET(A, B, C) \ 1115 A##_##B##_off = LoadStorePairOffsetFixed | A##_##B 1116 LOAD_STORE_PAIR_OP_LIST(LOAD_STORE_PAIR_OFFSET) 1117 #undef LOAD_STORE_PAIR_OFFSET 1118 }; 1119 1120 enum LoadStorePairNonTemporalOp : uint32_t { 1121 LoadStorePairNonTemporalFixed = 0x28000000, 1122 LoadStorePairNonTemporalFMask = 0x3B800000, 1123 LoadStorePairNonTemporalMask = 0xFFC00000, 1124 LoadStorePairNonTemporalLBit = 1 << 22, 1125 STNP_w = LoadStorePairNonTemporalFixed | STP_w, 1126 LDNP_w = LoadStorePairNonTemporalFixed | LDP_w, 1127 STNP_x = LoadStorePairNonTemporalFixed | STP_x, 1128 LDNP_x = LoadStorePairNonTemporalFixed | LDP_x, 1129 STNP_s = LoadStorePairNonTemporalFixed | STP_s, 1130 LDNP_s = LoadStorePairNonTemporalFixed | LDP_s, 1131 STNP_d = LoadStorePairNonTemporalFixed | STP_d, 1132 LDNP_d = LoadStorePairNonTemporalFixed | LDP_d, 1133 STNP_q = LoadStorePairNonTemporalFixed | STP_q, 1134 LDNP_q = LoadStorePairNonTemporalFixed | LDP_q 1135 }; 1136 1137 // Load with pointer authentication. 1138 enum LoadStorePACOp : uint32_t { 1139 LoadStorePACFixed = 0xF8200400, 1140 LoadStorePACFMask = 0xFF200400, 1141 LoadStorePACMask = 0xFFA00C00, 1142 LoadStorePACPreBit = 0x00000800, 1143 LDRAA = LoadStorePACFixed | 0x00000000, 1144 LDRAA_pre = LoadStorePACPreBit | LDRAA, 1145 LDRAB = LoadStorePACFixed | 0x00800000, 1146 LDRAB_pre = LoadStorePACPreBit | LDRAB 1147 }; 1148 1149 // Load literal. 1150 enum LoadLiteralOp : uint32_t { 1151 LoadLiteralFixed = 0x18000000, 1152 LoadLiteralFMask = 0x3B000000, 1153 LoadLiteralMask = 0xFF000000, 1154 LDR_w_lit = LoadLiteralFixed | 0x00000000, 1155 LDR_x_lit = LoadLiteralFixed | 0x40000000, 1156 LDRSW_x_lit = LoadLiteralFixed | 0x80000000, 1157 PRFM_lit = LoadLiteralFixed | 0xC0000000, 1158 LDR_s_lit = LoadLiteralFixed | 0x04000000, 1159 LDR_d_lit = LoadLiteralFixed | 0x44000000, 1160 LDR_q_lit = LoadLiteralFixed | 0x84000000 1161 }; 1162 1163 #define LOAD_STORE_OP_LIST(V) \ 1164 V(ST, RB, w, 0x00000000), \ 1165 V(ST, RH, w, 0x40000000), \ 1166 V(ST, R, w, 0x80000000), \ 1167 V(ST, R, x, 0xC0000000), \ 1168 V(LD, RB, w, 0x00400000), \ 1169 V(LD, RH, w, 0x40400000), \ 1170 V(LD, R, w, 0x80400000), \ 1171 V(LD, R, x, 0xC0400000), \ 1172 V(LD, RSB, x, 0x00800000), \ 1173 V(LD, RSH, x, 0x40800000), \ 1174 V(LD, RSW, x, 0x80800000), \ 1175 V(LD, RSB, w, 0x00C00000), \ 1176 V(LD, RSH, w, 0x40C00000), \ 1177 V(ST, R, b, 0x04000000), \ 1178 V(ST, R, h, 0x44000000), \ 1179 V(ST, R, s, 0x84000000), \ 1180 V(ST, R, d, 0xC4000000), \ 1181 V(ST, R, q, 0x04800000), \ 1182 V(LD, R, b, 0x04400000), \ 1183 V(LD, R, h, 0x44400000), \ 1184 V(LD, R, s, 0x84400000), \ 1185 V(LD, R, d, 0xC4400000), \ 1186 V(LD, R, q, 0x04C00000) 1187 1188 // Load/store (post, pre, offset and unsigned.) 1189 enum LoadStoreOp : uint32_t { 1190 LoadStoreMask = 0xC4C00000, 1191 LoadStoreVMask = 0x04000000, 1192 #define LOAD_STORE(A, B, C, D) \ 1193 A##B##_##C = D 1194 LOAD_STORE_OP_LIST(LOAD_STORE), 1195 #undef LOAD_STORE 1196 PRFM = 0xC0800000 1197 }; 1198 1199 // Load/store unscaled offset. 1200 enum LoadStoreUnscaledOffsetOp : uint32_t { 1201 LoadStoreUnscaledOffsetFixed = 0x38000000, 1202 LoadStoreUnscaledOffsetFMask = 0x3B200C00, 1203 LoadStoreUnscaledOffsetMask = 0xFFE00C00, 1204 PRFUM = LoadStoreUnscaledOffsetFixed | PRFM, 1205 #define LOAD_STORE_UNSCALED(A, B, C, D) \ 1206 A##U##B##_##C = LoadStoreUnscaledOffsetFixed | D 1207 LOAD_STORE_OP_LIST(LOAD_STORE_UNSCALED) 1208 #undef LOAD_STORE_UNSCALED 1209 }; 1210 1211 // Load/store post index. 1212 enum LoadStorePostIndex : uint32_t { 1213 LoadStorePostIndexFixed = 0x38000400, 1214 LoadStorePostIndexFMask = 0x3B200C00, 1215 LoadStorePostIndexMask = 0xFFE00C00, 1216 #define LOAD_STORE_POST_INDEX(A, B, C, D) \ 1217 A##B##_##C##_post = LoadStorePostIndexFixed | D 1218 LOAD_STORE_OP_LIST(LOAD_STORE_POST_INDEX) 1219 #undef LOAD_STORE_POST_INDEX 1220 }; 1221 1222 // Load/store pre index. 1223 enum LoadStorePreIndex : uint32_t { 1224 LoadStorePreIndexFixed = 0x38000C00, 1225 LoadStorePreIndexFMask = 0x3B200C00, 1226 LoadStorePreIndexMask = 0xFFE00C00, 1227 #define LOAD_STORE_PRE_INDEX(A, B, C, D) \ 1228 A##B##_##C##_pre = LoadStorePreIndexFixed | D 1229 LOAD_STORE_OP_LIST(LOAD_STORE_PRE_INDEX) 1230 #undef LOAD_STORE_PRE_INDEX 1231 }; 1232 1233 // Load/store unsigned offset. 1234 enum LoadStoreUnsignedOffset : uint32_t { 1235 LoadStoreUnsignedOffsetFixed = 0x39000000, 1236 LoadStoreUnsignedOffsetFMask = 0x3B000000, 1237 LoadStoreUnsignedOffsetMask = 0xFFC00000, 1238 PRFM_unsigned = LoadStoreUnsignedOffsetFixed | PRFM, 1239 #define LOAD_STORE_UNSIGNED_OFFSET(A, B, C, D) \ 1240 A##B##_##C##_unsigned = LoadStoreUnsignedOffsetFixed | D 1241 LOAD_STORE_OP_LIST(LOAD_STORE_UNSIGNED_OFFSET) 1242 #undef LOAD_STORE_UNSIGNED_OFFSET 1243 }; 1244 1245 // Load/store register offset. 1246 enum LoadStoreRegisterOffset : uint32_t { 1247 LoadStoreRegisterOffsetFixed = 0x38200800, 1248 LoadStoreRegisterOffsetFMask = 0x3B200C00, 1249 LoadStoreRegisterOffsetMask = 0xFFE00C00, 1250 PRFM_reg = LoadStoreRegisterOffsetFixed | PRFM, 1251 #define LOAD_STORE_REGISTER_OFFSET(A, B, C, D) \ 1252 A##B##_##C##_reg = LoadStoreRegisterOffsetFixed | D 1253 LOAD_STORE_OP_LIST(LOAD_STORE_REGISTER_OFFSET) 1254 #undef LOAD_STORE_REGISTER_OFFSET 1255 }; 1256 1257 enum LoadStoreExclusive : uint32_t { 1258 LoadStoreExclusiveFixed = 0x08000000, 1259 LoadStoreExclusiveFMask = 0x3F000000, 1260 LoadStoreExclusiveMask = 0xFFE08000, 1261 STXRB_w = LoadStoreExclusiveFixed | 0x00000000, 1262 STXRH_w = LoadStoreExclusiveFixed | 0x40000000, 1263 STXR_w = LoadStoreExclusiveFixed | 0x80000000, 1264 STXR_x = LoadStoreExclusiveFixed | 0xC0000000, 1265 LDXRB_w = LoadStoreExclusiveFixed | 0x00400000, 1266 LDXRH_w = LoadStoreExclusiveFixed | 0x40400000, 1267 LDXR_w = LoadStoreExclusiveFixed | 0x80400000, 1268 LDXR_x = LoadStoreExclusiveFixed | 0xC0400000, 1269 STXP_w = LoadStoreExclusiveFixed | 0x80200000, 1270 STXP_x = LoadStoreExclusiveFixed | 0xC0200000, 1271 LDXP_w = LoadStoreExclusiveFixed | 0x80600000, 1272 LDXP_x = LoadStoreExclusiveFixed | 0xC0600000, 1273 STLXRB_w = LoadStoreExclusiveFixed | 0x00008000, 1274 STLXRH_w = LoadStoreExclusiveFixed | 0x40008000, 1275 STLXR_w = LoadStoreExclusiveFixed | 0x80008000, 1276 STLXR_x = LoadStoreExclusiveFixed | 0xC0008000, 1277 LDAXRB_w = LoadStoreExclusiveFixed | 0x00408000, 1278 LDAXRH_w = LoadStoreExclusiveFixed | 0x40408000, 1279 LDAXR_w = LoadStoreExclusiveFixed | 0x80408000, 1280 LDAXR_x = LoadStoreExclusiveFixed | 0xC0408000, 1281 STLXP_w = LoadStoreExclusiveFixed | 0x80208000, 1282 STLXP_x = LoadStoreExclusiveFixed | 0xC0208000, 1283 LDAXP_w = LoadStoreExclusiveFixed | 0x80608000, 1284 LDAXP_x = LoadStoreExclusiveFixed | 0xC0608000, 1285 STLRB_w = LoadStoreExclusiveFixed | 0x00808000, 1286 STLRH_w = LoadStoreExclusiveFixed | 0x40808000, 1287 STLR_w = LoadStoreExclusiveFixed | 0x80808000, 1288 STLR_x = LoadStoreExclusiveFixed | 0xC0808000, 1289 LDARB_w = LoadStoreExclusiveFixed | 0x00C08000, 1290 LDARH_w = LoadStoreExclusiveFixed | 0x40C08000, 1291 LDAR_w = LoadStoreExclusiveFixed | 0x80C08000, 1292 LDAR_x = LoadStoreExclusiveFixed | 0xC0C08000, 1293 1294 // v8.1 Load/store LORegion ops 1295 STLLRB = LoadStoreExclusiveFixed | 0x00800000, 1296 LDLARB = LoadStoreExclusiveFixed | 0x00C00000, 1297 STLLRH = LoadStoreExclusiveFixed | 0x40800000, 1298 LDLARH = LoadStoreExclusiveFixed | 0x40C00000, 1299 STLLR_w = LoadStoreExclusiveFixed | 0x80800000, 1300 LDLAR_w = LoadStoreExclusiveFixed | 0x80C00000, 1301 STLLR_x = LoadStoreExclusiveFixed | 0xC0800000, 1302 LDLAR_x = LoadStoreExclusiveFixed | 0xC0C00000, 1303 1304 // v8.1 Load/store exclusive ops 1305 LSEBit_l = 0x00400000, 1306 LSEBit_o0 = 0x00008000, 1307 LSEBit_sz = 0x40000000, 1308 CASFixed = LoadStoreExclusiveFixed | 0x80A00000, 1309 CASBFixed = LoadStoreExclusiveFixed | 0x00A00000, 1310 CASHFixed = LoadStoreExclusiveFixed | 0x40A00000, 1311 CASPFixed = LoadStoreExclusiveFixed | 0x00200000, 1312 CAS_w = CASFixed, 1313 CAS_x = CASFixed | LSEBit_sz, 1314 CASA_w = CASFixed | LSEBit_l, 1315 CASA_x = CASFixed | LSEBit_l | LSEBit_sz, 1316 CASL_w = CASFixed | LSEBit_o0, 1317 CASL_x = CASFixed | LSEBit_o0 | LSEBit_sz, 1318 CASAL_w = CASFixed | LSEBit_l | LSEBit_o0, 1319 CASAL_x = CASFixed | LSEBit_l | LSEBit_o0 | LSEBit_sz, 1320 CASB = CASBFixed, 1321 CASAB = CASBFixed | LSEBit_l, 1322 CASLB = CASBFixed | LSEBit_o0, 1323 CASALB = CASBFixed | LSEBit_l | LSEBit_o0, 1324 CASH = CASHFixed, 1325 CASAH = CASHFixed | LSEBit_l, 1326 CASLH = CASHFixed | LSEBit_o0, 1327 CASALH = CASHFixed | LSEBit_l | LSEBit_o0, 1328 CASP_w = CASPFixed, 1329 CASP_x = CASPFixed | LSEBit_sz, 1330 CASPA_w = CASPFixed | LSEBit_l, 1331 CASPA_x = CASPFixed | LSEBit_l | LSEBit_sz, 1332 CASPL_w = CASPFixed | LSEBit_o0, 1333 CASPL_x = CASPFixed | LSEBit_o0 | LSEBit_sz, 1334 CASPAL_w = CASPFixed | LSEBit_l | LSEBit_o0, 1335 CASPAL_x = CASPFixed | LSEBit_l | LSEBit_o0 | LSEBit_sz 1336 }; 1337 1338 // Load/store RCpc unscaled offset. 1339 enum LoadStoreRCpcUnscaledOffsetOp : uint32_t { 1340 LoadStoreRCpcUnscaledOffsetFixed = 0x19000000, 1341 LoadStoreRCpcUnscaledOffsetFMask = 0x3F200C00, 1342 LoadStoreRCpcUnscaledOffsetMask = 0xFFE00C00, 1343 STLURB = LoadStoreRCpcUnscaledOffsetFixed | 0x00000000, 1344 LDAPURB = LoadStoreRCpcUnscaledOffsetFixed | 0x00400000, 1345 LDAPURSB_x = LoadStoreRCpcUnscaledOffsetFixed | 0x00800000, 1346 LDAPURSB_w = LoadStoreRCpcUnscaledOffsetFixed | 0x00C00000, 1347 STLURH = LoadStoreRCpcUnscaledOffsetFixed | 0x40000000, 1348 LDAPURH = LoadStoreRCpcUnscaledOffsetFixed | 0x40400000, 1349 LDAPURSH_x = LoadStoreRCpcUnscaledOffsetFixed | 0x40800000, 1350 LDAPURSH_w = LoadStoreRCpcUnscaledOffsetFixed | 0x40C00000, 1351 STLUR_w = LoadStoreRCpcUnscaledOffsetFixed | 0x80000000, 1352 LDAPUR_w = LoadStoreRCpcUnscaledOffsetFixed | 0x80400000, 1353 LDAPURSW = LoadStoreRCpcUnscaledOffsetFixed | 0x80800000, 1354 STLUR_x = LoadStoreRCpcUnscaledOffsetFixed | 0xC0000000, 1355 LDAPUR_x = LoadStoreRCpcUnscaledOffsetFixed | 0xC0400000 1356 }; 1357 1358 #define ATOMIC_MEMORY_SIMPLE_OPC_LIST(V) \ 1359 V(LDADD, 0x00000000), \ 1360 V(LDCLR, 0x00001000), \ 1361 V(LDEOR, 0x00002000), \ 1362 V(LDSET, 0x00003000), \ 1363 V(LDSMAX, 0x00004000), \ 1364 V(LDSMIN, 0x00005000), \ 1365 V(LDUMAX, 0x00006000), \ 1366 V(LDUMIN, 0x00007000) 1367 1368 // Atomic memory. 1369 enum AtomicMemoryOp : uint32_t { 1370 AtomicMemoryFixed = 0x38200000, 1371 AtomicMemoryFMask = 0x3B200C00, 1372 AtomicMemoryMask = 0xFFE0FC00, 1373 SWPB = AtomicMemoryFixed | 0x00008000, 1374 SWPAB = AtomicMemoryFixed | 0x00808000, 1375 SWPLB = AtomicMemoryFixed | 0x00408000, 1376 SWPALB = AtomicMemoryFixed | 0x00C08000, 1377 SWPH = AtomicMemoryFixed | 0x40008000, 1378 SWPAH = AtomicMemoryFixed | 0x40808000, 1379 SWPLH = AtomicMemoryFixed | 0x40408000, 1380 SWPALH = AtomicMemoryFixed | 0x40C08000, 1381 SWP_w = AtomicMemoryFixed | 0x80008000, 1382 SWPA_w = AtomicMemoryFixed | 0x80808000, 1383 SWPL_w = AtomicMemoryFixed | 0x80408000, 1384 SWPAL_w = AtomicMemoryFixed | 0x80C08000, 1385 SWP_x = AtomicMemoryFixed | 0xC0008000, 1386 SWPA_x = AtomicMemoryFixed | 0xC0808000, 1387 SWPL_x = AtomicMemoryFixed | 0xC0408000, 1388 SWPAL_x = AtomicMemoryFixed | 0xC0C08000, 1389 LDAPRB = AtomicMemoryFixed | 0x0080C000, 1390 LDAPRH = AtomicMemoryFixed | 0x4080C000, 1391 LDAPR_w = AtomicMemoryFixed | 0x8080C000, 1392 LDAPR_x = AtomicMemoryFixed | 0xC080C000, 1393 1394 AtomicMemorySimpleFMask = 0x3B208C00, 1395 AtomicMemorySimpleOpMask = 0x00007000, 1396 #define ATOMIC_MEMORY_SIMPLE(N, OP) \ 1397 N##Op = OP, \ 1398 N##B = AtomicMemoryFixed | OP, \ 1399 N##AB = AtomicMemoryFixed | OP | 0x00800000, \ 1400 N##LB = AtomicMemoryFixed | OP | 0x00400000, \ 1401 N##ALB = AtomicMemoryFixed | OP | 0x00C00000, \ 1402 N##H = AtomicMemoryFixed | OP | 0x40000000, \ 1403 N##AH = AtomicMemoryFixed | OP | 0x40800000, \ 1404 N##LH = AtomicMemoryFixed | OP | 0x40400000, \ 1405 N##ALH = AtomicMemoryFixed | OP | 0x40C00000, \ 1406 N##_w = AtomicMemoryFixed | OP | 0x80000000, \ 1407 N##A_w = AtomicMemoryFixed | OP | 0x80800000, \ 1408 N##L_w = AtomicMemoryFixed | OP | 0x80400000, \ 1409 N##AL_w = AtomicMemoryFixed | OP | 0x80C00000, \ 1410 N##_x = AtomicMemoryFixed | OP | 0xC0000000, \ 1411 N##A_x = AtomicMemoryFixed | OP | 0xC0800000, \ 1412 N##L_x = AtomicMemoryFixed | OP | 0xC0400000, \ 1413 N##AL_x = AtomicMemoryFixed | OP | 0xC0C00000 1414 1415 ATOMIC_MEMORY_SIMPLE_OPC_LIST(ATOMIC_MEMORY_SIMPLE) 1416 #undef ATOMIC_MEMORY_SIMPLE 1417 }; 1418 1419 // Conditional compare. 1420 enum ConditionalCompareOp : uint32_t { 1421 ConditionalCompareMask = 0x60000000, 1422 CCMN = 0x20000000, 1423 CCMP = 0x60000000 1424 }; 1425 1426 // Conditional compare register. 1427 enum ConditionalCompareRegisterOp : uint32_t { 1428 ConditionalCompareRegisterFixed = 0x1A400000, 1429 ConditionalCompareRegisterFMask = 0x1FE00800, 1430 ConditionalCompareRegisterMask = 0xFFE00C10, 1431 CCMN_w = ConditionalCompareRegisterFixed | CCMN, 1432 CCMN_x = ConditionalCompareRegisterFixed | SixtyFourBits | CCMN, 1433 CCMP_w = ConditionalCompareRegisterFixed | CCMP, 1434 CCMP_x = ConditionalCompareRegisterFixed | SixtyFourBits | CCMP 1435 }; 1436 1437 // Conditional compare immediate. 1438 enum ConditionalCompareImmediateOp : uint32_t { 1439 ConditionalCompareImmediateFixed = 0x1A400800, 1440 ConditionalCompareImmediateFMask = 0x1FE00800, 1441 ConditionalCompareImmediateMask = 0xFFE00C10, 1442 CCMN_w_imm = ConditionalCompareImmediateFixed | CCMN, 1443 CCMN_x_imm = ConditionalCompareImmediateFixed | SixtyFourBits | CCMN, 1444 CCMP_w_imm = ConditionalCompareImmediateFixed | CCMP, 1445 CCMP_x_imm = ConditionalCompareImmediateFixed | SixtyFourBits | CCMP 1446 }; 1447 1448 // Conditional select. 1449 enum ConditionalSelectOp : uint32_t { 1450 ConditionalSelectFixed = 0x1A800000, 1451 ConditionalSelectFMask = 0x1FE00000, 1452 ConditionalSelectMask = 0xFFE00C00, 1453 CSEL_w = ConditionalSelectFixed | 0x00000000, 1454 CSEL_x = ConditionalSelectFixed | 0x80000000, 1455 CSEL = CSEL_w, 1456 CSINC_w = ConditionalSelectFixed | 0x00000400, 1457 CSINC_x = ConditionalSelectFixed | 0x80000400, 1458 CSINC = CSINC_w, 1459 CSINV_w = ConditionalSelectFixed | 0x40000000, 1460 CSINV_x = ConditionalSelectFixed | 0xC0000000, 1461 CSINV = CSINV_w, 1462 CSNEG_w = ConditionalSelectFixed | 0x40000400, 1463 CSNEG_x = ConditionalSelectFixed | 0xC0000400, 1464 CSNEG = CSNEG_w 1465 }; 1466 1467 // Data processing 1 source. 1468 enum DataProcessing1SourceOp : uint32_t { 1469 DataProcessing1SourceFixed = 0x5AC00000, 1470 DataProcessing1SourceFMask = 0x5FE00000, 1471 DataProcessing1SourceMask = 0xFFFFFC00, 1472 RBIT = DataProcessing1SourceFixed | 0x00000000, 1473 RBIT_w = RBIT, 1474 RBIT_x = RBIT | SixtyFourBits, 1475 REV16 = DataProcessing1SourceFixed | 0x00000400, 1476 REV16_w = REV16, 1477 REV16_x = REV16 | SixtyFourBits, 1478 REV = DataProcessing1SourceFixed | 0x00000800, 1479 REV_w = REV, 1480 REV32_x = REV | SixtyFourBits, 1481 REV_x = DataProcessing1SourceFixed | SixtyFourBits | 0x00000C00, 1482 CLZ = DataProcessing1SourceFixed | 0x00001000, 1483 CLZ_w = CLZ, 1484 CLZ_x = CLZ | SixtyFourBits, 1485 CLS = DataProcessing1SourceFixed | 0x00001400, 1486 CLS_w = CLS, 1487 CLS_x = CLS | SixtyFourBits, 1488 1489 // Pointer authentication instructions in Armv8.3. 1490 PACIA = DataProcessing1SourceFixed | 0x80010000, 1491 PACIB = DataProcessing1SourceFixed | 0x80010400, 1492 PACDA = DataProcessing1SourceFixed | 0x80010800, 1493 PACDB = DataProcessing1SourceFixed | 0x80010C00, 1494 AUTIA = DataProcessing1SourceFixed | 0x80011000, 1495 AUTIB = DataProcessing1SourceFixed | 0x80011400, 1496 AUTDA = DataProcessing1SourceFixed | 0x80011800, 1497 AUTDB = DataProcessing1SourceFixed | 0x80011C00, 1498 PACIZA = DataProcessing1SourceFixed | 0x80012000, 1499 PACIZB = DataProcessing1SourceFixed | 0x80012400, 1500 PACDZA = DataProcessing1SourceFixed | 0x80012800, 1501 PACDZB = DataProcessing1SourceFixed | 0x80012C00, 1502 AUTIZA = DataProcessing1SourceFixed | 0x80013000, 1503 AUTIZB = DataProcessing1SourceFixed | 0x80013400, 1504 AUTDZA = DataProcessing1SourceFixed | 0x80013800, 1505 AUTDZB = DataProcessing1SourceFixed | 0x80013C00, 1506 XPACI = DataProcessing1SourceFixed | 0x80014000, 1507 XPACD = DataProcessing1SourceFixed | 0x80014400, 1508 1509 // Mozilla change: Add constants for CSSC instructions. 1510 ABS = DataProcessing1SourceFixed | 0x0000'2000, 1511 ABS_w = ABS, 1512 ABS_x = ABS | SixtyFourBits, 1513 CNT = DataProcessing1SourceFixed | 0x0000'1C00, 1514 CNT_w = CNT, 1515 CNT_x = CNT | SixtyFourBits, 1516 CTZ = DataProcessing1SourceFixed | 0x0000'1800, 1517 CTZ_w = CTZ, 1518 CTZ_x = CTZ | SixtyFourBits, 1519 }; 1520 1521 // Data processing 2 source. 1522 enum DataProcessing2SourceOp : uint32_t { 1523 DataProcessing2SourceFixed = 0x1AC00000, 1524 DataProcessing2SourceFMask = 0x5FE00000, 1525 DataProcessing2SourceMask = 0xFFE0FC00, 1526 UDIV_w = DataProcessing2SourceFixed | 0x00000800, 1527 UDIV_x = DataProcessing2SourceFixed | 0x80000800, 1528 UDIV = UDIV_w, 1529 SDIV_w = DataProcessing2SourceFixed | 0x00000C00, 1530 SDIV_x = DataProcessing2SourceFixed | 0x80000C00, 1531 SDIV = SDIV_w, 1532 LSLV_w = DataProcessing2SourceFixed | 0x00002000, 1533 LSLV_x = DataProcessing2SourceFixed | 0x80002000, 1534 LSLV = LSLV_w, 1535 LSRV_w = DataProcessing2SourceFixed | 0x00002400, 1536 LSRV_x = DataProcessing2SourceFixed | 0x80002400, 1537 LSRV = LSRV_w, 1538 ASRV_w = DataProcessing2SourceFixed | 0x00002800, 1539 ASRV_x = DataProcessing2SourceFixed | 0x80002800, 1540 ASRV = ASRV_w, 1541 RORV_w = DataProcessing2SourceFixed | 0x00002C00, 1542 RORV_x = DataProcessing2SourceFixed | 0x80002C00, 1543 RORV = RORV_w, 1544 PACGA = DataProcessing2SourceFixed | SixtyFourBits | 0x00003000, 1545 CRC32B = DataProcessing2SourceFixed | 0x00004000, 1546 CRC32H = DataProcessing2SourceFixed | 0x00004400, 1547 CRC32W = DataProcessing2SourceFixed | 0x00004800, 1548 CRC32X = DataProcessing2SourceFixed | SixtyFourBits | 0x00004C00, 1549 CRC32CB = DataProcessing2SourceFixed | 0x00005000, 1550 CRC32CH = DataProcessing2SourceFixed | 0x00005400, 1551 CRC32CW = DataProcessing2SourceFixed | 0x00005800, 1552 CRC32CX = DataProcessing2SourceFixed | SixtyFourBits | 0x00005C00, 1553 1554 // Mozilla change: Add constants for CSSC instructions. 1555 SMAX = DataProcessing2SourceFixed | 0x0000'6000, 1556 SMAX_w = SMAX, 1557 SMAX_x = SMAX | SixtyFourBits, 1558 SMIN = DataProcessing2SourceFixed | 0x0000'6800, 1559 SMIN_w = SMIN, 1560 SMIN_x = SMIN | SixtyFourBits, 1561 UMAX = DataProcessing2SourceFixed | 0x0000'6400, 1562 UMAX_w = UMAX, 1563 UMAX_x = UMAX | SixtyFourBits, 1564 UMIN = DataProcessing2SourceFixed | 0x0000'6C00, 1565 UMIN_w = UMIN, 1566 UMIN_x = UMIN | SixtyFourBits, 1567 }; 1568 1569 // Data processing 3 source. 1570 enum DataProcessing3SourceOp : uint32_t { 1571 DataProcessing3SourceFixed = 0x1B000000, 1572 DataProcessing3SourceFMask = 0x1F000000, 1573 DataProcessing3SourceMask = 0xFFE08000, 1574 MADD_w = DataProcessing3SourceFixed | 0x00000000, 1575 MADD_x = DataProcessing3SourceFixed | 0x80000000, 1576 MADD = MADD_w, 1577 MSUB_w = DataProcessing3SourceFixed | 0x00008000, 1578 MSUB_x = DataProcessing3SourceFixed | 0x80008000, 1579 MSUB = MSUB_w, 1580 SMADDL_x = DataProcessing3SourceFixed | 0x80200000, 1581 SMSUBL_x = DataProcessing3SourceFixed | 0x80208000, 1582 SMULH_x = DataProcessing3SourceFixed | 0x80400000, 1583 UMADDL_x = DataProcessing3SourceFixed | 0x80A00000, 1584 UMSUBL_x = DataProcessing3SourceFixed | 0x80A08000, 1585 UMULH_x = DataProcessing3SourceFixed | 0x80C00000 1586 }; 1587 1588 // Floating point compare. 1589 enum FPCompareOp : uint32_t { 1590 FPCompareFixed = 0x1E202000, 1591 FPCompareFMask = 0x5F203C00, 1592 FPCompareMask = 0xFFE0FC1F, 1593 FCMP_h = FPCompareFixed | FP16 | 0x00000000, 1594 FCMP_s = FPCompareFixed | 0x00000000, 1595 FCMP_d = FPCompareFixed | FP64 | 0x00000000, 1596 FCMP = FCMP_s, 1597 FCMP_h_zero = FPCompareFixed | FP16 | 0x00000008, 1598 FCMP_s_zero = FPCompareFixed | 0x00000008, 1599 FCMP_d_zero = FPCompareFixed | FP64 | 0x00000008, 1600 FCMP_zero = FCMP_s_zero, 1601 FCMPE_h = FPCompareFixed | FP16 | 0x00000010, 1602 FCMPE_s = FPCompareFixed | 0x00000010, 1603 FCMPE_d = FPCompareFixed | FP64 | 0x00000010, 1604 FCMPE = FCMPE_s, 1605 FCMPE_h_zero = FPCompareFixed | FP16 | 0x00000018, 1606 FCMPE_s_zero = FPCompareFixed | 0x00000018, 1607 FCMPE_d_zero = FPCompareFixed | FP64 | 0x00000018, 1608 FCMPE_zero = FCMPE_s_zero 1609 }; 1610 1611 // Floating point conditional compare. 1612 enum FPConditionalCompareOp : uint32_t { 1613 FPConditionalCompareFixed = 0x1E200400, 1614 FPConditionalCompareFMask = 0x5F200C00, 1615 FPConditionalCompareMask = 0xFFE00C10, 1616 FCCMP_h = FPConditionalCompareFixed | FP16 | 0x00000000, 1617 FCCMP_s = FPConditionalCompareFixed | 0x00000000, 1618 FCCMP_d = FPConditionalCompareFixed | FP64 | 0x00000000, 1619 FCCMP = FCCMP_s, 1620 FCCMPE_h = FPConditionalCompareFixed | FP16 | 0x00000010, 1621 FCCMPE_s = FPConditionalCompareFixed | 0x00000010, 1622 FCCMPE_d = FPConditionalCompareFixed | FP64 | 0x00000010, 1623 FCCMPE = FCCMPE_s 1624 }; 1625 1626 // Floating point conditional select. 1627 enum FPConditionalSelectOp : uint32_t { 1628 FPConditionalSelectFixed = 0x1E200C00, 1629 FPConditionalSelectFMask = 0x5F200C00, 1630 FPConditionalSelectMask = 0xFFE00C00, 1631 FCSEL_h = FPConditionalSelectFixed | FP16 | 0x00000000, 1632 FCSEL_s = FPConditionalSelectFixed | 0x00000000, 1633 FCSEL_d = FPConditionalSelectFixed | FP64 | 0x00000000, 1634 FCSEL = FCSEL_s 1635 }; 1636 1637 // Floating point immediate. 1638 enum FPImmediateOp : uint32_t { 1639 FPImmediateFixed = 0x1E201000, 1640 FPImmediateFMask = 0x5F201C00, 1641 FPImmediateMask = 0xFFE01C00, 1642 FMOV_h_imm = FPImmediateFixed | FP16 | 0x00000000, 1643 FMOV_s_imm = FPImmediateFixed | 0x00000000, 1644 FMOV_d_imm = FPImmediateFixed | FP64 | 0x00000000 1645 }; 1646 1647 // Floating point data processing 1 source. 1648 enum FPDataProcessing1SourceOp : uint32_t { 1649 FPDataProcessing1SourceFixed = 0x1E204000, 1650 FPDataProcessing1SourceFMask = 0x5F207C00, 1651 FPDataProcessing1SourceMask = 0xFFFFFC00, 1652 FMOV_h = FPDataProcessing1SourceFixed | FP16 | 0x00000000, 1653 FMOV_s = FPDataProcessing1SourceFixed | 0x00000000, 1654 FMOV_d = FPDataProcessing1SourceFixed | FP64 | 0x00000000, 1655 FMOV = FMOV_s, 1656 FABS_h = FPDataProcessing1SourceFixed | FP16 | 0x00008000, 1657 FABS_s = FPDataProcessing1SourceFixed | 0x00008000, 1658 FABS_d = FPDataProcessing1SourceFixed | FP64 | 0x00008000, 1659 FABS = FABS_s, 1660 FNEG_h = FPDataProcessing1SourceFixed | FP16 | 0x00010000, 1661 FNEG_s = FPDataProcessing1SourceFixed | 0x00010000, 1662 FNEG_d = FPDataProcessing1SourceFixed | FP64 | 0x00010000, 1663 FNEG = FNEG_s, 1664 FSQRT_h = FPDataProcessing1SourceFixed | FP16 | 0x00018000, 1665 FSQRT_s = FPDataProcessing1SourceFixed | 0x00018000, 1666 FSQRT_d = FPDataProcessing1SourceFixed | FP64 | 0x00018000, 1667 FSQRT = FSQRT_s, 1668 FCVT_ds = FPDataProcessing1SourceFixed | 0x00028000, 1669 FCVT_sd = FPDataProcessing1SourceFixed | FP64 | 0x00020000, 1670 FCVT_hs = FPDataProcessing1SourceFixed | 0x00038000, 1671 FCVT_hd = FPDataProcessing1SourceFixed | FP64 | 0x00038000, 1672 FCVT_sh = FPDataProcessing1SourceFixed | 0x00C20000, 1673 FCVT_dh = FPDataProcessing1SourceFixed | 0x00C28000, 1674 FRINT32X_s = FPDataProcessing1SourceFixed | 0x00088000, 1675 FRINT32X_d = FPDataProcessing1SourceFixed | FP64 | 0x00088000, 1676 FRINT32X = FRINT32X_s, 1677 FRINT32Z_s = FPDataProcessing1SourceFixed | 0x00080000, 1678 FRINT32Z_d = FPDataProcessing1SourceFixed | FP64 | 0x00080000, 1679 FRINT32Z = FRINT32Z_s, 1680 FRINT64X_s = FPDataProcessing1SourceFixed | 0x00098000, 1681 FRINT64X_d = FPDataProcessing1SourceFixed | FP64 | 0x00098000, 1682 FRINT64X = FRINT64X_s, 1683 FRINT64Z_s = FPDataProcessing1SourceFixed | 0x00090000, 1684 FRINT64Z_d = FPDataProcessing1SourceFixed | FP64 | 0x00090000, 1685 FRINT64Z = FRINT64Z_s, 1686 FRINTN_h = FPDataProcessing1SourceFixed | FP16 | 0x00040000, 1687 FRINTN_s = FPDataProcessing1SourceFixed | 0x00040000, 1688 FRINTN_d = FPDataProcessing1SourceFixed | FP64 | 0x00040000, 1689 FRINTN = FRINTN_s, 1690 FRINTP_h = FPDataProcessing1SourceFixed | FP16 | 0x00048000, 1691 FRINTP_s = FPDataProcessing1SourceFixed | 0x00048000, 1692 FRINTP_d = FPDataProcessing1SourceFixed | FP64 | 0x00048000, 1693 FRINTP = FRINTP_s, 1694 FRINTM_h = FPDataProcessing1SourceFixed | FP16 | 0x00050000, 1695 FRINTM_s = FPDataProcessing1SourceFixed | 0x00050000, 1696 FRINTM_d = FPDataProcessing1SourceFixed | FP64 | 0x00050000, 1697 FRINTM = FRINTM_s, 1698 FRINTZ_h = FPDataProcessing1SourceFixed | FP16 | 0x00058000, 1699 FRINTZ_s = FPDataProcessing1SourceFixed | 0x00058000, 1700 FRINTZ_d = FPDataProcessing1SourceFixed | FP64 | 0x00058000, 1701 FRINTZ = FRINTZ_s, 1702 FRINTA_h = FPDataProcessing1SourceFixed | FP16 | 0x00060000, 1703 FRINTA_s = FPDataProcessing1SourceFixed | 0x00060000, 1704 FRINTA_d = FPDataProcessing1SourceFixed | FP64 | 0x00060000, 1705 FRINTA = FRINTA_s, 1706 FRINTX_h = FPDataProcessing1SourceFixed | FP16 | 0x00070000, 1707 FRINTX_s = FPDataProcessing1SourceFixed | 0x00070000, 1708 FRINTX_d = FPDataProcessing1SourceFixed | FP64 | 0x00070000, 1709 FRINTX = FRINTX_s, 1710 FRINTI_h = FPDataProcessing1SourceFixed | FP16 | 0x00078000, 1711 FRINTI_s = FPDataProcessing1SourceFixed | 0x00078000, 1712 FRINTI_d = FPDataProcessing1SourceFixed | FP64 | 0x00078000, 1713 FRINTI = FRINTI_s 1714 }; 1715 1716 // Floating point data processing 2 source. 1717 enum FPDataProcessing2SourceOp : uint32_t { 1718 FPDataProcessing2SourceFixed = 0x1E200800, 1719 FPDataProcessing2SourceFMask = 0x5F200C00, 1720 FPDataProcessing2SourceMask = 0xFFE0FC00, 1721 FMUL = FPDataProcessing2SourceFixed | 0x00000000, 1722 FMUL_h = FMUL | FP16, 1723 FMUL_s = FMUL, 1724 FMUL_d = FMUL | FP64, 1725 FDIV = FPDataProcessing2SourceFixed | 0x00001000, 1726 FDIV_h = FDIV | FP16, 1727 FDIV_s = FDIV, 1728 FDIV_d = FDIV | FP64, 1729 FADD = FPDataProcessing2SourceFixed | 0x00002000, 1730 FADD_h = FADD | FP16, 1731 FADD_s = FADD, 1732 FADD_d = FADD | FP64, 1733 FSUB = FPDataProcessing2SourceFixed | 0x00003000, 1734 FSUB_h = FSUB | FP16, 1735 FSUB_s = FSUB, 1736 FSUB_d = FSUB | FP64, 1737 FMAX = FPDataProcessing2SourceFixed | 0x00004000, 1738 FMAX_h = FMAX | FP16, 1739 FMAX_s = FMAX, 1740 FMAX_d = FMAX | FP64, 1741 FMIN = FPDataProcessing2SourceFixed | 0x00005000, 1742 FMIN_h = FMIN | FP16, 1743 FMIN_s = FMIN, 1744 FMIN_d = FMIN | FP64, 1745 FMAXNM = FPDataProcessing2SourceFixed | 0x00006000, 1746 FMAXNM_h = FMAXNM | FP16, 1747 FMAXNM_s = FMAXNM, 1748 FMAXNM_d = FMAXNM | FP64, 1749 FMINNM = FPDataProcessing2SourceFixed | 0x00007000, 1750 FMINNM_h = FMINNM | FP16, 1751 FMINNM_s = FMINNM, 1752 FMINNM_d = FMINNM | FP64, 1753 FNMUL = FPDataProcessing2SourceFixed | 0x00008000, 1754 FNMUL_h = FNMUL | FP16, 1755 FNMUL_s = FNMUL, 1756 FNMUL_d = FNMUL | FP64 1757 }; 1758 1759 // Floating point data processing 3 source. 1760 enum FPDataProcessing3SourceOp : uint32_t { 1761 FPDataProcessing3SourceFixed = 0x1F000000, 1762 FPDataProcessing3SourceFMask = 0x5F000000, 1763 FPDataProcessing3SourceMask = 0xFFE08000, 1764 FMADD_h = FPDataProcessing3SourceFixed | 0x00C00000, 1765 FMSUB_h = FPDataProcessing3SourceFixed | 0x00C08000, 1766 FNMADD_h = FPDataProcessing3SourceFixed | 0x00E00000, 1767 FNMSUB_h = FPDataProcessing3SourceFixed | 0x00E08000, 1768 FMADD_s = FPDataProcessing3SourceFixed | 0x00000000, 1769 FMSUB_s = FPDataProcessing3SourceFixed | 0x00008000, 1770 FNMADD_s = FPDataProcessing3SourceFixed | 0x00200000, 1771 FNMSUB_s = FPDataProcessing3SourceFixed | 0x00208000, 1772 FMADD_d = FPDataProcessing3SourceFixed | 0x00400000, 1773 FMSUB_d = FPDataProcessing3SourceFixed | 0x00408000, 1774 FNMADD_d = FPDataProcessing3SourceFixed | 0x00600000, 1775 FNMSUB_d = FPDataProcessing3SourceFixed | 0x00608000 1776 }; 1777 1778 // Conversion between floating point and integer. 1779 enum FPIntegerConvertOp : uint32_t { 1780 FPIntegerConvertFixed = 0x1E200000, 1781 FPIntegerConvertFMask = 0x5F20FC00, 1782 FPIntegerConvertMask = 0xFFFFFC00, 1783 FCVTNS = FPIntegerConvertFixed | 0x00000000, 1784 FCVTNS_wh = FCVTNS | FP16, 1785 FCVTNS_xh = FCVTNS | SixtyFourBits | FP16, 1786 FCVTNS_ws = FCVTNS, 1787 FCVTNS_xs = FCVTNS | SixtyFourBits, 1788 FCVTNS_wd = FCVTNS | FP64, 1789 FCVTNS_xd = FCVTNS | SixtyFourBits | FP64, 1790 FCVTNU = FPIntegerConvertFixed | 0x00010000, 1791 FCVTNU_wh = FCVTNU | FP16, 1792 FCVTNU_xh = FCVTNU | SixtyFourBits | FP16, 1793 FCVTNU_ws = FCVTNU, 1794 FCVTNU_xs = FCVTNU | SixtyFourBits, 1795 FCVTNU_wd = FCVTNU | FP64, 1796 FCVTNU_xd = FCVTNU | SixtyFourBits | FP64, 1797 FCVTPS = FPIntegerConvertFixed | 0x00080000, 1798 FCVTPS_wh = FCVTPS | FP16, 1799 FCVTPS_xh = FCVTPS | SixtyFourBits | FP16, 1800 FCVTPS_ws = FCVTPS, 1801 FCVTPS_xs = FCVTPS | SixtyFourBits, 1802 FCVTPS_wd = FCVTPS | FP64, 1803 FCVTPS_xd = FCVTPS | SixtyFourBits | FP64, 1804 FCVTPU = FPIntegerConvertFixed | 0x00090000, 1805 FCVTPU_wh = FCVTPU | FP16, 1806 FCVTPU_xh = FCVTPU | SixtyFourBits | FP16, 1807 FCVTPU_ws = FCVTPU, 1808 FCVTPU_xs = FCVTPU | SixtyFourBits, 1809 FCVTPU_wd = FCVTPU | FP64, 1810 FCVTPU_xd = FCVTPU | SixtyFourBits | FP64, 1811 FCVTMS = FPIntegerConvertFixed | 0x00100000, 1812 FCVTMS_wh = FCVTMS | FP16, 1813 FCVTMS_xh = FCVTMS | SixtyFourBits | FP16, 1814 FCVTMS_ws = FCVTMS, 1815 FCVTMS_xs = FCVTMS | SixtyFourBits, 1816 FCVTMS_wd = FCVTMS | FP64, 1817 FCVTMS_xd = FCVTMS | SixtyFourBits | FP64, 1818 FCVTMU = FPIntegerConvertFixed | 0x00110000, 1819 FCVTMU_wh = FCVTMU | FP16, 1820 FCVTMU_xh = FCVTMU | SixtyFourBits | FP16, 1821 FCVTMU_ws = FCVTMU, 1822 FCVTMU_xs = FCVTMU | SixtyFourBits, 1823 FCVTMU_wd = FCVTMU | FP64, 1824 FCVTMU_xd = FCVTMU | SixtyFourBits | FP64, 1825 FCVTZS = FPIntegerConvertFixed | 0x00180000, 1826 FCVTZS_wh = FCVTZS | FP16, 1827 FCVTZS_xh = FCVTZS | SixtyFourBits | FP16, 1828 FCVTZS_ws = FCVTZS, 1829 FCVTZS_xs = FCVTZS | SixtyFourBits, 1830 FCVTZS_wd = FCVTZS | FP64, 1831 FCVTZS_xd = FCVTZS | SixtyFourBits | FP64, 1832 FCVTZU = FPIntegerConvertFixed | 0x00190000, 1833 FCVTZU_wh = FCVTZU | FP16, 1834 FCVTZU_xh = FCVTZU | SixtyFourBits | FP16, 1835 FCVTZU_ws = FCVTZU, 1836 FCVTZU_xs = FCVTZU | SixtyFourBits, 1837 FCVTZU_wd = FCVTZU | FP64, 1838 FCVTZU_xd = FCVTZU | SixtyFourBits | FP64, 1839 SCVTF = FPIntegerConvertFixed | 0x00020000, 1840 SCVTF_hw = SCVTF | FP16, 1841 SCVTF_hx = SCVTF | SixtyFourBits | FP16, 1842 SCVTF_sw = SCVTF, 1843 SCVTF_sx = SCVTF | SixtyFourBits, 1844 SCVTF_dw = SCVTF | FP64, 1845 SCVTF_dx = SCVTF | SixtyFourBits | FP64, 1846 UCVTF = FPIntegerConvertFixed | 0x00030000, 1847 UCVTF_hw = UCVTF | FP16, 1848 UCVTF_hx = UCVTF | SixtyFourBits | FP16, 1849 UCVTF_sw = UCVTF, 1850 UCVTF_sx = UCVTF | SixtyFourBits, 1851 UCVTF_dw = UCVTF | FP64, 1852 UCVTF_dx = UCVTF | SixtyFourBits | FP64, 1853 FCVTAS = FPIntegerConvertFixed | 0x00040000, 1854 FCVTAS_wh = FCVTAS | FP16, 1855 FCVTAS_xh = FCVTAS | SixtyFourBits | FP16, 1856 FCVTAS_ws = FCVTAS, 1857 FCVTAS_xs = FCVTAS | SixtyFourBits, 1858 FCVTAS_wd = FCVTAS | FP64, 1859 FCVTAS_xd = FCVTAS | SixtyFourBits | FP64, 1860 FCVTAU = FPIntegerConvertFixed | 0x00050000, 1861 FCVTAU_wh = FCVTAU | FP16, 1862 FCVTAU_xh = FCVTAU | SixtyFourBits | FP16, 1863 FCVTAU_ws = FCVTAU, 1864 FCVTAU_xs = FCVTAU | SixtyFourBits, 1865 FCVTAU_wd = FCVTAU | FP64, 1866 FCVTAU_xd = FCVTAU | SixtyFourBits | FP64, 1867 FMOV_wh = FPIntegerConvertFixed | 0x00060000 | FP16, 1868 FMOV_hw = FPIntegerConvertFixed | 0x00070000 | FP16, 1869 FMOV_xh = FMOV_wh | SixtyFourBits, 1870 FMOV_hx = FMOV_hw | SixtyFourBits, 1871 FMOV_ws = FPIntegerConvertFixed | 0x00060000, 1872 FMOV_sw = FPIntegerConvertFixed | 0x00070000, 1873 FMOV_xd = FMOV_ws | SixtyFourBits | FP64, 1874 FMOV_dx = FMOV_sw | SixtyFourBits | FP64, 1875 FMOV_d1_x = FPIntegerConvertFixed | SixtyFourBits | 0x008F0000, 1876 FMOV_x_d1 = FPIntegerConvertFixed | SixtyFourBits | 0x008E0000, 1877 FJCVTZS = FPIntegerConvertFixed | FP64 | 0x001E0000 1878 }; 1879 1880 // Conversion between fixed point and floating point. 1881 enum FPFixedPointConvertOp : uint32_t { 1882 FPFixedPointConvertFixed = 0x1E000000, 1883 FPFixedPointConvertFMask = 0x5F200000, 1884 FPFixedPointConvertMask = 0xFFFF0000, 1885 FCVTZS_fixed = FPFixedPointConvertFixed | 0x00180000, 1886 FCVTZS_wh_fixed = FCVTZS_fixed | FP16, 1887 FCVTZS_xh_fixed = FCVTZS_fixed | SixtyFourBits | FP16, 1888 FCVTZS_ws_fixed = FCVTZS_fixed, 1889 FCVTZS_xs_fixed = FCVTZS_fixed | SixtyFourBits, 1890 FCVTZS_wd_fixed = FCVTZS_fixed | FP64, 1891 FCVTZS_xd_fixed = FCVTZS_fixed | SixtyFourBits | FP64, 1892 FCVTZU_fixed = FPFixedPointConvertFixed | 0x00190000, 1893 FCVTZU_wh_fixed = FCVTZU_fixed | FP16, 1894 FCVTZU_xh_fixed = FCVTZU_fixed | SixtyFourBits | FP16, 1895 FCVTZU_ws_fixed = FCVTZU_fixed, 1896 FCVTZU_xs_fixed = FCVTZU_fixed | SixtyFourBits, 1897 FCVTZU_wd_fixed = FCVTZU_fixed | FP64, 1898 FCVTZU_xd_fixed = FCVTZU_fixed | SixtyFourBits | FP64, 1899 SCVTF_fixed = FPFixedPointConvertFixed | 0x00020000, 1900 SCVTF_hw_fixed = SCVTF_fixed | FP16, 1901 SCVTF_hx_fixed = SCVTF_fixed | SixtyFourBits | FP16, 1902 SCVTF_sw_fixed = SCVTF_fixed, 1903 SCVTF_sx_fixed = SCVTF_fixed | SixtyFourBits, 1904 SCVTF_dw_fixed = SCVTF_fixed | FP64, 1905 SCVTF_dx_fixed = SCVTF_fixed | SixtyFourBits | FP64, 1906 UCVTF_fixed = FPFixedPointConvertFixed | 0x00030000, 1907 UCVTF_hw_fixed = UCVTF_fixed | FP16, 1908 UCVTF_hx_fixed = UCVTF_fixed | SixtyFourBits | FP16, 1909 UCVTF_sw_fixed = UCVTF_fixed, 1910 UCVTF_sx_fixed = UCVTF_fixed | SixtyFourBits, 1911 UCVTF_dw_fixed = UCVTF_fixed | FP64, 1912 UCVTF_dx_fixed = UCVTF_fixed | SixtyFourBits | FP64 1913 }; 1914 1915 // Crypto - two register SHA. 1916 enum Crypto2RegSHAOp : uint32_t { 1917 Crypto2RegSHAFixed = 0x5E280800, 1918 Crypto2RegSHAFMask = 0xFF3E0C00 1919 }; 1920 1921 // Crypto - three register SHA. 1922 enum Crypto3RegSHAOp : uint32_t { 1923 Crypto3RegSHAFixed = 0x5E000000, 1924 Crypto3RegSHAFMask = 0xFF208C00 1925 }; 1926 1927 // Crypto - AES. 1928 enum CryptoAESOp : uint32_t { 1929 CryptoAESFixed = 0x4E280800, 1930 CryptoAESFMask = 0xFF3E0C00 1931 }; 1932 1933 // NEON instructions with two register operands. 1934 enum NEON2RegMiscOp : uint32_t { 1935 NEON2RegMiscFixed = 0x0E200800, 1936 NEON2RegMiscFMask = 0x9F3E0C00, 1937 NEON2RegMiscMask = 0xBF3FFC00, 1938 NEON2RegMiscUBit = 0x20000000, 1939 NEON_REV64 = NEON2RegMiscFixed | 0x00000000, 1940 NEON_REV32 = NEON2RegMiscFixed | 0x20000000, 1941 NEON_REV16 = NEON2RegMiscFixed | 0x00001000, 1942 NEON_SADDLP = NEON2RegMiscFixed | 0x00002000, 1943 NEON_UADDLP = NEON_SADDLP | NEON2RegMiscUBit, 1944 NEON_SUQADD = NEON2RegMiscFixed | 0x00003000, 1945 NEON_USQADD = NEON_SUQADD | NEON2RegMiscUBit, 1946 NEON_CLS = NEON2RegMiscFixed | 0x00004000, 1947 NEON_CLZ = NEON2RegMiscFixed | 0x20004000, 1948 NEON_CNT = NEON2RegMiscFixed | 0x00005000, 1949 NEON_RBIT_NOT = NEON2RegMiscFixed | 0x20005000, 1950 NEON_SADALP = NEON2RegMiscFixed | 0x00006000, 1951 NEON_UADALP = NEON_SADALP | NEON2RegMiscUBit, 1952 NEON_SQABS = NEON2RegMiscFixed | 0x00007000, 1953 NEON_SQNEG = NEON2RegMiscFixed | 0x20007000, 1954 NEON_CMGT_zero = NEON2RegMiscFixed | 0x00008000, 1955 NEON_CMGE_zero = NEON2RegMiscFixed | 0x20008000, 1956 NEON_CMEQ_zero = NEON2RegMiscFixed | 0x00009000, 1957 NEON_CMLE_zero = NEON2RegMiscFixed | 0x20009000, 1958 NEON_CMLT_zero = NEON2RegMiscFixed | 0x0000A000, 1959 NEON_ABS = NEON2RegMiscFixed | 0x0000B000, 1960 NEON_NEG = NEON2RegMiscFixed | 0x2000B000, 1961 NEON_XTN = NEON2RegMiscFixed | 0x00012000, 1962 NEON_SQXTUN = NEON2RegMiscFixed | 0x20012000, 1963 NEON_SHLL = NEON2RegMiscFixed | 0x20013000, 1964 NEON_SQXTN = NEON2RegMiscFixed | 0x00014000, 1965 NEON_UQXTN = NEON_SQXTN | NEON2RegMiscUBit, 1966 1967 NEON2RegMiscOpcode = 0x0001F000, 1968 NEON_RBIT_NOT_opcode = NEON_RBIT_NOT & NEON2RegMiscOpcode, 1969 NEON_NEG_opcode = NEON_NEG & NEON2RegMiscOpcode, 1970 NEON_XTN_opcode = NEON_XTN & NEON2RegMiscOpcode, 1971 NEON_UQXTN_opcode = NEON_UQXTN & NEON2RegMiscOpcode, 1972 1973 // These instructions use only one bit of the size field. The other bit is 1974 // used to distinguish between instructions. 1975 NEON2RegMiscFPMask = NEON2RegMiscMask | 0x00800000, 1976 NEON_FABS = NEON2RegMiscFixed | 0x0080F000, 1977 NEON_FNEG = NEON2RegMiscFixed | 0x2080F000, 1978 NEON_FCVTN = NEON2RegMiscFixed | 0x00016000, 1979 NEON_FCVTXN = NEON2RegMiscFixed | 0x20016000, 1980 NEON_FCVTL = NEON2RegMiscFixed | 0x00017000, 1981 NEON_FRINT32X = NEON2RegMiscFixed | 0x2001E000, 1982 NEON_FRINT32Z = NEON2RegMiscFixed | 0x0001E000, 1983 NEON_FRINT64X = NEON2RegMiscFixed | 0x2001F000, 1984 NEON_FRINT64Z = NEON2RegMiscFixed | 0x0001F000, 1985 NEON_FRINTN = NEON2RegMiscFixed | 0x00018000, 1986 NEON_FRINTA = NEON2RegMiscFixed | 0x20018000, 1987 NEON_FRINTP = NEON2RegMiscFixed | 0x00818000, 1988 NEON_FRINTM = NEON2RegMiscFixed | 0x00019000, 1989 NEON_FRINTX = NEON2RegMiscFixed | 0x20019000, 1990 NEON_FRINTZ = NEON2RegMiscFixed | 0x00819000, 1991 NEON_FRINTI = NEON2RegMiscFixed | 0x20819000, 1992 NEON_FCVTNS = NEON2RegMiscFixed | 0x0001A000, 1993 NEON_FCVTNU = NEON_FCVTNS | NEON2RegMiscUBit, 1994 NEON_FCVTPS = NEON2RegMiscFixed | 0x0081A000, 1995 NEON_FCVTPU = NEON_FCVTPS | NEON2RegMiscUBit, 1996 NEON_FCVTMS = NEON2RegMiscFixed | 0x0001B000, 1997 NEON_FCVTMU = NEON_FCVTMS | NEON2RegMiscUBit, 1998 NEON_FCVTZS = NEON2RegMiscFixed | 0x0081B000, 1999 NEON_FCVTZU = NEON_FCVTZS | NEON2RegMiscUBit, 2000 NEON_FCVTAS = NEON2RegMiscFixed | 0x0001C000, 2001 NEON_FCVTAU = NEON_FCVTAS | NEON2RegMiscUBit, 2002 NEON_FSQRT = NEON2RegMiscFixed | 0x2081F000, 2003 NEON_SCVTF = NEON2RegMiscFixed | 0x0001D000, 2004 NEON_UCVTF = NEON_SCVTF | NEON2RegMiscUBit, 2005 NEON_URSQRTE = NEON2RegMiscFixed | 0x2081C000, 2006 NEON_URECPE = NEON2RegMiscFixed | 0x0081C000, 2007 NEON_FRSQRTE = NEON2RegMiscFixed | 0x2081D000, 2008 NEON_FRECPE = NEON2RegMiscFixed | 0x0081D000, 2009 NEON_FCMGT_zero = NEON2RegMiscFixed | 0x0080C000, 2010 NEON_FCMGE_zero = NEON2RegMiscFixed | 0x2080C000, 2011 NEON_FCMEQ_zero = NEON2RegMiscFixed | 0x0080D000, 2012 NEON_FCMLE_zero = NEON2RegMiscFixed | 0x2080D000, 2013 NEON_FCMLT_zero = NEON2RegMiscFixed | 0x0080E000, 2014 2015 NEON_FCVTL_opcode = NEON_FCVTL & NEON2RegMiscOpcode, 2016 NEON_FCVTN_opcode = NEON_FCVTN & NEON2RegMiscOpcode 2017 }; 2018 2019 // NEON instructions with two register operands (FP16). 2020 enum NEON2RegMiscFP16Op : uint32_t { 2021 NEON2RegMiscFP16Fixed = 0x0E780800, 2022 NEON2RegMiscFP16FMask = 0x9F7E0C00, 2023 NEON2RegMiscFP16Mask = 0xBFFFFC00, 2024 NEON_FRINTN_H = NEON2RegMiscFP16Fixed | 0x00018000, 2025 NEON_FRINTM_H = NEON2RegMiscFP16Fixed | 0x00019000, 2026 NEON_FCVTNS_H = NEON2RegMiscFP16Fixed | 0x0001A000, 2027 NEON_FCVTMS_H = NEON2RegMiscFP16Fixed | 0x0001B000, 2028 NEON_FCVTAS_H = NEON2RegMiscFP16Fixed | 0x0001C000, 2029 NEON_SCVTF_H = NEON2RegMiscFP16Fixed | 0x0001D000, 2030 NEON_FCMGT_H_zero = NEON2RegMiscFP16Fixed | 0x0080C000, 2031 NEON_FCMEQ_H_zero = NEON2RegMiscFP16Fixed | 0x0080D000, 2032 NEON_FCMLT_H_zero = NEON2RegMiscFP16Fixed | 0x0080E000, 2033 NEON_FABS_H = NEON2RegMiscFP16Fixed | 0x0080F000, 2034 NEON_FRINTP_H = NEON2RegMiscFP16Fixed | 0x00818000, 2035 NEON_FRINTZ_H = NEON2RegMiscFP16Fixed | 0x00819000, 2036 NEON_FCVTPS_H = NEON2RegMiscFP16Fixed | 0x0081A000, 2037 NEON_FCVTZS_H = NEON2RegMiscFP16Fixed | 0x0081B000, 2038 NEON_FRECPE_H = NEON2RegMiscFP16Fixed | 0x0081D000, 2039 NEON_FRINTA_H = NEON2RegMiscFP16Fixed | 0x20018000, 2040 NEON_FRINTX_H = NEON2RegMiscFP16Fixed | 0x20019000, 2041 NEON_FCVTNU_H = NEON2RegMiscFP16Fixed | 0x2001A000, 2042 NEON_FCVTMU_H = NEON2RegMiscFP16Fixed | 0x2001B000, 2043 NEON_FCVTAU_H = NEON2RegMiscFP16Fixed | 0x2001C000, 2044 NEON_UCVTF_H = NEON2RegMiscFP16Fixed | 0x2001D000, 2045 NEON_FCMGE_H_zero = NEON2RegMiscFP16Fixed | 0x2080C000, 2046 NEON_FCMLE_H_zero = NEON2RegMiscFP16Fixed | 0x2080D000, 2047 NEON_FNEG_H = NEON2RegMiscFP16Fixed | 0x2080F000, 2048 NEON_FRINTI_H = NEON2RegMiscFP16Fixed | 0x20819000, 2049 NEON_FCVTPU_H = NEON2RegMiscFP16Fixed | 0x2081A000, 2050 NEON_FCVTZU_H = NEON2RegMiscFP16Fixed | 0x2081B000, 2051 NEON_FRSQRTE_H = NEON2RegMiscFP16Fixed | 0x2081D000, 2052 NEON_FSQRT_H = NEON2RegMiscFP16Fixed | 0x2081F000 2053 }; 2054 2055 // NEON instructions with three same-type operands. 2056 enum NEON3SameOp : uint32_t { 2057 NEON3SameFixed = 0x0E200400, 2058 NEON3SameFMask = 0x9F200400, 2059 NEON3SameMask = 0xBF20FC00, 2060 NEON3SameUBit = 0x20000000, 2061 NEON_ADD = NEON3SameFixed | 0x00008000, 2062 NEON_ADDP = NEON3SameFixed | 0x0000B800, 2063 NEON_SHADD = NEON3SameFixed | 0x00000000, 2064 NEON_SHSUB = NEON3SameFixed | 0x00002000, 2065 NEON_SRHADD = NEON3SameFixed | 0x00001000, 2066 NEON_CMEQ = NEON3SameFixed | NEON3SameUBit | 0x00008800, 2067 NEON_CMGE = NEON3SameFixed | 0x00003800, 2068 NEON_CMGT = NEON3SameFixed | 0x00003000, 2069 NEON_CMHI = NEON3SameFixed | NEON3SameUBit | NEON_CMGT, 2070 NEON_CMHS = NEON3SameFixed | NEON3SameUBit | NEON_CMGE, 2071 NEON_CMTST = NEON3SameFixed | 0x00008800, 2072 NEON_MLA = NEON3SameFixed | 0x00009000, 2073 NEON_MLS = NEON3SameFixed | 0x20009000, 2074 NEON_MUL = NEON3SameFixed | 0x00009800, 2075 NEON_PMUL = NEON3SameFixed | 0x20009800, 2076 NEON_SRSHL = NEON3SameFixed | 0x00005000, 2077 NEON_SQSHL = NEON3SameFixed | 0x00004800, 2078 NEON_SQRSHL = NEON3SameFixed | 0x00005800, 2079 NEON_SSHL = NEON3SameFixed | 0x00004000, 2080 NEON_SMAX = NEON3SameFixed | 0x00006000, 2081 NEON_SMAXP = NEON3SameFixed | 0x0000A000, 2082 NEON_SMIN = NEON3SameFixed | 0x00006800, 2083 NEON_SMINP = NEON3SameFixed | 0x0000A800, 2084 NEON_SABD = NEON3SameFixed | 0x00007000, 2085 NEON_SABA = NEON3SameFixed | 0x00007800, 2086 NEON_UABD = NEON3SameFixed | NEON3SameUBit | NEON_SABD, 2087 NEON_UABA = NEON3SameFixed | NEON3SameUBit | NEON_SABA, 2088 NEON_SQADD = NEON3SameFixed | 0x00000800, 2089 NEON_SQSUB = NEON3SameFixed | 0x00002800, 2090 NEON_SUB = NEON3SameFixed | NEON3SameUBit | 0x00008000, 2091 NEON_UHADD = NEON3SameFixed | NEON3SameUBit | NEON_SHADD, 2092 NEON_UHSUB = NEON3SameFixed | NEON3SameUBit | NEON_SHSUB, 2093 NEON_URHADD = NEON3SameFixed | NEON3SameUBit | NEON_SRHADD, 2094 NEON_UMAX = NEON3SameFixed | NEON3SameUBit | NEON_SMAX, 2095 NEON_UMAXP = NEON3SameFixed | NEON3SameUBit | NEON_SMAXP, 2096 NEON_UMIN = NEON3SameFixed | NEON3SameUBit | NEON_SMIN, 2097 NEON_UMINP = NEON3SameFixed | NEON3SameUBit | NEON_SMINP, 2098 NEON_URSHL = NEON3SameFixed | NEON3SameUBit | NEON_SRSHL, 2099 NEON_UQADD = NEON3SameFixed | NEON3SameUBit | NEON_SQADD, 2100 NEON_UQRSHL = NEON3SameFixed | NEON3SameUBit | NEON_SQRSHL, 2101 NEON_UQSHL = NEON3SameFixed | NEON3SameUBit | NEON_SQSHL, 2102 NEON_UQSUB = NEON3SameFixed | NEON3SameUBit | NEON_SQSUB, 2103 NEON_USHL = NEON3SameFixed | NEON3SameUBit | NEON_SSHL, 2104 NEON_SQDMULH = NEON3SameFixed | 0x0000B000, 2105 NEON_SQRDMULH = NEON3SameFixed | 0x2000B000, 2106 2107 // NEON floating point instructions with three same-type operands. 2108 NEON3SameFPFixed = NEON3SameFixed | 0x0000C000, 2109 NEON3SameFPFMask = NEON3SameFMask | 0x0000C000, 2110 NEON3SameFPMask = NEON3SameMask | 0x00800000, 2111 NEON_FADD = NEON3SameFixed | 0x0000D000, 2112 NEON_FSUB = NEON3SameFixed | 0x0080D000, 2113 NEON_FMUL = NEON3SameFixed | 0x2000D800, 2114 NEON_FDIV = NEON3SameFixed | 0x2000F800, 2115 NEON_FMAX = NEON3SameFixed | 0x0000F000, 2116 NEON_FMAXNM = NEON3SameFixed | 0x0000C000, 2117 NEON_FMAXP = NEON3SameFixed | 0x2000F000, 2118 NEON_FMAXNMP = NEON3SameFixed | 0x2000C000, 2119 NEON_FMIN = NEON3SameFixed | 0x0080F000, 2120 NEON_FMINNM = NEON3SameFixed | 0x0080C000, 2121 NEON_FMINP = NEON3SameFixed | 0x2080F000, 2122 NEON_FMINNMP = NEON3SameFixed | 0x2080C000, 2123 NEON_FMLA = NEON3SameFixed | 0x0000C800, 2124 NEON_FMLS = NEON3SameFixed | 0x0080C800, 2125 NEON_FMULX = NEON3SameFixed | 0x0000D800, 2126 NEON_FRECPS = NEON3SameFixed | 0x0000F800, 2127 NEON_FRSQRTS = NEON3SameFixed | 0x0080F800, 2128 NEON_FABD = NEON3SameFixed | 0x2080D000, 2129 NEON_FADDP = NEON3SameFixed | 0x2000D000, 2130 NEON_FCMEQ = NEON3SameFixed | 0x0000E000, 2131 NEON_FCMGE = NEON3SameFixed | 0x2000E000, 2132 NEON_FCMGT = NEON3SameFixed | 0x2080E000, 2133 NEON_FACGE = NEON3SameFixed | 0x2000E800, 2134 NEON_FACGT = NEON3SameFixed | 0x2080E800, 2135 2136 // NEON logical instructions with three same-type operands. 2137 NEON3SameLogicalFixed = NEON3SameFixed | 0x00001800, 2138 NEON3SameLogicalFMask = NEON3SameFMask | 0x0000F800, 2139 NEON3SameLogicalMask = 0xBFE0FC00, 2140 NEON3SameLogicalFormatMask = NEON_Q, 2141 NEON_AND = NEON3SameLogicalFixed | 0x00000000, 2142 NEON_ORR = NEON3SameLogicalFixed | 0x00A00000, 2143 NEON_ORN = NEON3SameLogicalFixed | 0x00C00000, 2144 NEON_EOR = NEON3SameLogicalFixed | 0x20000000, 2145 NEON_BIC = NEON3SameLogicalFixed | 0x00400000, 2146 NEON_BIF = NEON3SameLogicalFixed | 0x20C00000, 2147 NEON_BIT = NEON3SameLogicalFixed | 0x20800000, 2148 NEON_BSL = NEON3SameLogicalFixed | 0x20400000, 2149 2150 // FHM (FMLAL-like) instructions have an oddball encoding scheme under 3Same. 2151 NEON3SameFHMMask = 0xBFE0FC00, // U size opcode 2152 NEON_FMLAL = NEON3SameFixed | 0x0000E800, // 0 00 11101 2153 NEON_FMLAL2 = NEON3SameFixed | 0x2000C800, // 1 00 11001 2154 NEON_FMLSL = NEON3SameFixed | 0x0080E800, // 0 10 11101 2155 NEON_FMLSL2 = NEON3SameFixed | 0x2080C800 // 1 10 11001 2156 }; 2157 2158 2159 enum NEON3SameFP16 : uint32_t { 2160 NEON3SameFP16Fixed = 0x0E400400, 2161 NEON3SameFP16FMask = 0x9F60C400, 2162 NEON3SameFP16Mask = 0xBFE0FC00, 2163 NEON_FMAXNM_H = NEON3SameFP16Fixed | 0x00000000, 2164 NEON_FMLA_H = NEON3SameFP16Fixed | 0x00000800, 2165 NEON_FADD_H = NEON3SameFP16Fixed | 0x00001000, 2166 NEON_FMULX_H = NEON3SameFP16Fixed | 0x00001800, 2167 NEON_FCMEQ_H = NEON3SameFP16Fixed | 0x00002000, 2168 NEON_FMAX_H = NEON3SameFP16Fixed | 0x00003000, 2169 NEON_FRECPS_H = NEON3SameFP16Fixed | 0x00003800, 2170 NEON_FMINNM_H = NEON3SameFP16Fixed | 0x00800000, 2171 NEON_FMLS_H = NEON3SameFP16Fixed | 0x00800800, 2172 NEON_FSUB_H = NEON3SameFP16Fixed | 0x00801000, 2173 NEON_FMIN_H = NEON3SameFP16Fixed | 0x00803000, 2174 NEON_FRSQRTS_H = NEON3SameFP16Fixed | 0x00803800, 2175 NEON_FMAXNMP_H = NEON3SameFP16Fixed | 0x20000000, 2176 NEON_FADDP_H = NEON3SameFP16Fixed | 0x20001000, 2177 NEON_FMUL_H = NEON3SameFP16Fixed | 0x20001800, 2178 NEON_FCMGE_H = NEON3SameFP16Fixed | 0x20002000, 2179 NEON_FACGE_H = NEON3SameFP16Fixed | 0x20002800, 2180 NEON_FMAXP_H = NEON3SameFP16Fixed | 0x20003000, 2181 NEON_FDIV_H = NEON3SameFP16Fixed | 0x20003800, 2182 NEON_FMINNMP_H = NEON3SameFP16Fixed | 0x20800000, 2183 NEON_FABD_H = NEON3SameFP16Fixed | 0x20801000, 2184 NEON_FCMGT_H = NEON3SameFP16Fixed | 0x20802000, 2185 NEON_FACGT_H = NEON3SameFP16Fixed | 0x20802800, 2186 NEON_FMINP_H = NEON3SameFP16Fixed | 0x20803000 2187 }; 2188 2189 2190 // 'Extra' NEON instructions with three same-type operands. 2191 enum NEON3SameExtraOp : uint32_t { 2192 NEON3SameExtraFixed = 0x0E008400, 2193 NEON3SameExtraUBit = 0x20000000, 2194 NEON3SameExtraFMask = 0x9E208400, 2195 NEON3SameExtraMask = 0xBE20FC00, 2196 NEON_SQRDMLAH = NEON3SameExtraFixed | NEON3SameExtraUBit, 2197 NEON_SQRDMLSH = NEON3SameExtraFixed | NEON3SameExtraUBit | 0x00000800, 2198 NEON_SDOT = NEON3SameExtraFixed | 0x00001000, 2199 NEON_UDOT = NEON3SameExtraFixed | NEON3SameExtraUBit | 0x00001000, 2200 2201 /* v8.3 Complex Numbers */ 2202 NEON3SameExtraFCFixed = 0x2E00C400, 2203 NEON3SameExtraFCFMask = 0xBF20C400, 2204 // FCMLA fixes opcode<3:2>, and uses opcode<1:0> to encode <rotate>. 2205 NEON3SameExtraFCMLAMask = NEON3SameExtraFCFMask | 0x00006000, 2206 NEON_FCMLA = NEON3SameExtraFCFixed, 2207 // FCADD fixes opcode<3:2, 0>, and uses opcode<1> to encode <rotate>. 2208 NEON3SameExtraFCADDMask = NEON3SameExtraFCFMask | 0x00006800, 2209 NEON_FCADD = NEON3SameExtraFCFixed | 0x00002000 2210 // Other encodings under NEON3SameExtraFCFMask are UNALLOCATED. 2211 }; 2212 2213 // NEON instructions with three different-type operands. 2214 enum NEON3DifferentOp : uint32_t { 2215 NEON3DifferentFixed = 0x0E200000, 2216 NEON3DifferentFMask = 0x9F200C00, 2217 NEON3DifferentMask = 0xFF20FC00, 2218 NEON_ADDHN = NEON3DifferentFixed | 0x00004000, 2219 NEON_ADDHN2 = NEON_ADDHN | NEON_Q, 2220 NEON_PMULL = NEON3DifferentFixed | 0x0000E000, 2221 NEON_PMULL2 = NEON_PMULL | NEON_Q, 2222 NEON_RADDHN = NEON3DifferentFixed | 0x20004000, 2223 NEON_RADDHN2 = NEON_RADDHN | NEON_Q, 2224 NEON_RSUBHN = NEON3DifferentFixed | 0x20006000, 2225 NEON_RSUBHN2 = NEON_RSUBHN | NEON_Q, 2226 NEON_SABAL = NEON3DifferentFixed | 0x00005000, 2227 NEON_SABAL2 = NEON_SABAL | NEON_Q, 2228 NEON_SABDL = NEON3DifferentFixed | 0x00007000, 2229 NEON_SABDL2 = NEON_SABDL | NEON_Q, 2230 NEON_SADDL = NEON3DifferentFixed | 0x00000000, 2231 NEON_SADDL2 = NEON_SADDL | NEON_Q, 2232 NEON_SADDW = NEON3DifferentFixed | 0x00001000, 2233 NEON_SADDW2 = NEON_SADDW | NEON_Q, 2234 NEON_SMLAL = NEON3DifferentFixed | 0x00008000, 2235 NEON_SMLAL2 = NEON_SMLAL | NEON_Q, 2236 NEON_SMLSL = NEON3DifferentFixed | 0x0000A000, 2237 NEON_SMLSL2 = NEON_SMLSL | NEON_Q, 2238 NEON_SMULL = NEON3DifferentFixed | 0x0000C000, 2239 NEON_SMULL2 = NEON_SMULL | NEON_Q, 2240 NEON_SSUBL = NEON3DifferentFixed | 0x00002000, 2241 NEON_SSUBL2 = NEON_SSUBL | NEON_Q, 2242 NEON_SSUBW = NEON3DifferentFixed | 0x00003000, 2243 NEON_SSUBW2 = NEON_SSUBW | NEON_Q, 2244 NEON_SQDMLAL = NEON3DifferentFixed | 0x00009000, 2245 NEON_SQDMLAL2 = NEON_SQDMLAL | NEON_Q, 2246 NEON_SQDMLSL = NEON3DifferentFixed | 0x0000B000, 2247 NEON_SQDMLSL2 = NEON_SQDMLSL | NEON_Q, 2248 NEON_SQDMULL = NEON3DifferentFixed | 0x0000D000, 2249 NEON_SQDMULL2 = NEON_SQDMULL | NEON_Q, 2250 NEON_SUBHN = NEON3DifferentFixed | 0x00006000, 2251 NEON_SUBHN2 = NEON_SUBHN | NEON_Q, 2252 NEON_UABAL = NEON_SABAL | NEON3SameUBit, 2253 NEON_UABAL2 = NEON_UABAL | NEON_Q, 2254 NEON_UABDL = NEON_SABDL | NEON3SameUBit, 2255 NEON_UABDL2 = NEON_UABDL | NEON_Q, 2256 NEON_UADDL = NEON_SADDL | NEON3SameUBit, 2257 NEON_UADDL2 = NEON_UADDL | NEON_Q, 2258 NEON_UADDW = NEON_SADDW | NEON3SameUBit, 2259 NEON_UADDW2 = NEON_UADDW | NEON_Q, 2260 NEON_UMLAL = NEON_SMLAL | NEON3SameUBit, 2261 NEON_UMLAL2 = NEON_UMLAL | NEON_Q, 2262 NEON_UMLSL = NEON_SMLSL | NEON3SameUBit, 2263 NEON_UMLSL2 = NEON_UMLSL | NEON_Q, 2264 NEON_UMULL = NEON_SMULL | NEON3SameUBit, 2265 NEON_UMULL2 = NEON_UMULL | NEON_Q, 2266 NEON_USUBL = NEON_SSUBL | NEON3SameUBit, 2267 NEON_USUBL2 = NEON_USUBL | NEON_Q, 2268 NEON_USUBW = NEON_SSUBW | NEON3SameUBit, 2269 NEON_USUBW2 = NEON_USUBW | NEON_Q 2270 }; 2271 2272 // NEON instructions operating across vectors. 2273 enum NEONAcrossLanesOp : uint32_t { 2274 NEONAcrossLanesFixed = 0x0E300800, 2275 NEONAcrossLanesFMask = 0x9F3E0C00, 2276 NEONAcrossLanesMask = 0xBF3FFC00, 2277 NEON_ADDV = NEONAcrossLanesFixed | 0x0001B000, 2278 NEON_SADDLV = NEONAcrossLanesFixed | 0x00003000, 2279 NEON_UADDLV = NEONAcrossLanesFixed | 0x20003000, 2280 NEON_SMAXV = NEONAcrossLanesFixed | 0x0000A000, 2281 NEON_SMINV = NEONAcrossLanesFixed | 0x0001A000, 2282 NEON_UMAXV = NEONAcrossLanesFixed | 0x2000A000, 2283 NEON_UMINV = NEONAcrossLanesFixed | 0x2001A000, 2284 2285 NEONAcrossLanesFP16Fixed = NEONAcrossLanesFixed | 0x0000C000, 2286 NEONAcrossLanesFP16FMask = NEONAcrossLanesFMask | 0x2000C000, 2287 NEONAcrossLanesFP16Mask = NEONAcrossLanesMask | 0x20800000, 2288 NEON_FMAXNMV_H = NEONAcrossLanesFP16Fixed | 0x00000000, 2289 NEON_FMAXV_H = NEONAcrossLanesFP16Fixed | 0x00003000, 2290 NEON_FMINNMV_H = NEONAcrossLanesFP16Fixed | 0x00800000, 2291 NEON_FMINV_H = NEONAcrossLanesFP16Fixed | 0x00803000, 2292 2293 // NEON floating point across instructions. 2294 NEONAcrossLanesFPFixed = NEONAcrossLanesFixed | 0x2000C000, 2295 NEONAcrossLanesFPFMask = NEONAcrossLanesFMask | 0x2000C000, 2296 NEONAcrossLanesFPMask = NEONAcrossLanesMask | 0x20800000, 2297 2298 NEON_FMAXV = NEONAcrossLanesFPFixed | 0x2000F000, 2299 NEON_FMINV = NEONAcrossLanesFPFixed | 0x2080F000, 2300 NEON_FMAXNMV = NEONAcrossLanesFPFixed | 0x2000C000, 2301 NEON_FMINNMV = NEONAcrossLanesFPFixed | 0x2080C000 2302 }; 2303 2304 // NEON instructions with indexed element operand. 2305 enum NEONByIndexedElementOp : uint32_t { 2306 NEONByIndexedElementFixed = 0x0F000000, 2307 NEONByIndexedElementFMask = 0x9F000400, 2308 NEONByIndexedElementMask = 0xBF00F400, 2309 NEON_MUL_byelement = NEONByIndexedElementFixed | 0x00008000, 2310 NEON_MLA_byelement = NEONByIndexedElementFixed | 0x20000000, 2311 NEON_MLS_byelement = NEONByIndexedElementFixed | 0x20004000, 2312 NEON_SMULL_byelement = NEONByIndexedElementFixed | 0x0000A000, 2313 NEON_SMLAL_byelement = NEONByIndexedElementFixed | 0x00002000, 2314 NEON_SMLSL_byelement = NEONByIndexedElementFixed | 0x00006000, 2315 NEON_UMULL_byelement = NEONByIndexedElementFixed | 0x2000A000, 2316 NEON_UMLAL_byelement = NEONByIndexedElementFixed | 0x20002000, 2317 NEON_UMLSL_byelement = NEONByIndexedElementFixed | 0x20006000, 2318 NEON_SQDMULL_byelement = NEONByIndexedElementFixed | 0x0000B000, 2319 NEON_SQDMLAL_byelement = NEONByIndexedElementFixed | 0x00003000, 2320 NEON_SQDMLSL_byelement = NEONByIndexedElementFixed | 0x00007000, 2321 NEON_SQDMULH_byelement = NEONByIndexedElementFixed | 0x0000C000, 2322 NEON_SQRDMULH_byelement = NEONByIndexedElementFixed | 0x0000D000, 2323 NEON_SDOT_byelement = NEONByIndexedElementFixed | 0x0000E000, 2324 NEON_SQRDMLAH_byelement = NEONByIndexedElementFixed | 0x2000D000, 2325 NEON_UDOT_byelement = NEONByIndexedElementFixed | 0x2000E000, 2326 NEON_SQRDMLSH_byelement = NEONByIndexedElementFixed | 0x2000F000, 2327 2328 NEON_FMLA_H_byelement = NEONByIndexedElementFixed | 0x00001000, 2329 NEON_FMLS_H_byelement = NEONByIndexedElementFixed | 0x00005000, 2330 NEON_FMUL_H_byelement = NEONByIndexedElementFixed | 0x00009000, 2331 NEON_FMULX_H_byelement = NEONByIndexedElementFixed | 0x20009000, 2332 2333 // Floating point instructions. 2334 NEONByIndexedElementFPFixed = NEONByIndexedElementFixed | 0x00800000, 2335 NEONByIndexedElementFPMask = NEONByIndexedElementMask | 0x00800000, 2336 NEON_FMLA_byelement = NEONByIndexedElementFPFixed | 0x00001000, 2337 NEON_FMLS_byelement = NEONByIndexedElementFPFixed | 0x00005000, 2338 NEON_FMUL_byelement = NEONByIndexedElementFPFixed | 0x00009000, 2339 NEON_FMULX_byelement = NEONByIndexedElementFPFixed | 0x20009000, 2340 2341 // FMLAL-like instructions. 2342 // For all cases: U = x, size = 10, opcode = xx00 2343 NEONByIndexedElementFPLongFixed = NEONByIndexedElementFixed | 0x00800000, 2344 NEONByIndexedElementFPLongFMask = NEONByIndexedElementFMask | 0x00C03000, 2345 NEONByIndexedElementFPLongMask = 0xBFC0F400, 2346 NEON_FMLAL_H_byelement = NEONByIndexedElementFixed | 0x00800000, 2347 NEON_FMLAL2_H_byelement = NEONByIndexedElementFixed | 0x20808000, 2348 NEON_FMLSL_H_byelement = NEONByIndexedElementFixed | 0x00804000, 2349 NEON_FMLSL2_H_byelement = NEONByIndexedElementFixed | 0x2080C000, 2350 2351 // Complex instruction(s). 2352 // This is necessary because the 'rot' encoding moves into the 2353 // NEONByIndex..Mask space. 2354 NEONByIndexedElementFPComplexMask = 0xBF009400, 2355 NEON_FCMLA_byelement = NEONByIndexedElementFixed | 0x20001000 2356 }; 2357 2358 // NEON register copy. 2359 enum NEONCopyOp : uint32_t { 2360 NEONCopyFixed = 0x0E000400, 2361 NEONCopyFMask = 0x9FE08400, 2362 NEONCopyMask = 0x3FE08400, 2363 NEONCopyInsElementMask = NEONCopyMask | 0x40000000, 2364 NEONCopyInsGeneralMask = NEONCopyMask | 0x40007800, 2365 NEONCopyDupElementMask = NEONCopyMask | 0x20007800, 2366 NEONCopyDupGeneralMask = NEONCopyDupElementMask, 2367 NEONCopyUmovMask = NEONCopyMask | 0x20007800, 2368 NEONCopySmovMask = NEONCopyMask | 0x20007800, 2369 NEON_INS_ELEMENT = NEONCopyFixed | 0x60000000, 2370 NEON_INS_GENERAL = NEONCopyFixed | 0x40001800, 2371 NEON_DUP_ELEMENT = NEONCopyFixed | 0x00000000, 2372 NEON_DUP_GENERAL = NEONCopyFixed | 0x00000800, 2373 NEON_SMOV = NEONCopyFixed | 0x00002800, 2374 NEON_UMOV = NEONCopyFixed | 0x00003800 2375 }; 2376 2377 // NEON extract. 2378 enum NEONExtractOp : uint32_t { 2379 NEONExtractFixed = 0x2E000000, 2380 NEONExtractFMask = 0xBF208400, 2381 NEONExtractMask = 0xBFE08400, 2382 NEON_EXT = NEONExtractFixed | 0x00000000 2383 }; 2384 2385 enum NEONLoadStoreMultiOp : uint32_t { 2386 NEONLoadStoreMultiL = 0x00400000, 2387 NEONLoadStoreMulti1_1v = 0x00007000, 2388 NEONLoadStoreMulti1_2v = 0x0000A000, 2389 NEONLoadStoreMulti1_3v = 0x00006000, 2390 NEONLoadStoreMulti1_4v = 0x00002000, 2391 NEONLoadStoreMulti2 = 0x00008000, 2392 NEONLoadStoreMulti3 = 0x00004000, 2393 NEONLoadStoreMulti4 = 0x00000000 2394 }; 2395 2396 // NEON load/store multiple structures. 2397 enum NEONLoadStoreMultiStructOp : uint32_t { 2398 NEONLoadStoreMultiStructFixed = 0x0C000000, 2399 NEONLoadStoreMultiStructFMask = 0xBFBF0000, 2400 NEONLoadStoreMultiStructMask = 0xBFFFF000, 2401 NEONLoadStoreMultiStructStore = NEONLoadStoreMultiStructFixed, 2402 NEONLoadStoreMultiStructLoad = NEONLoadStoreMultiStructFixed | 2403 NEONLoadStoreMultiL, 2404 NEON_LD1_1v = NEONLoadStoreMultiStructLoad | NEONLoadStoreMulti1_1v, 2405 NEON_LD1_2v = NEONLoadStoreMultiStructLoad | NEONLoadStoreMulti1_2v, 2406 NEON_LD1_3v = NEONLoadStoreMultiStructLoad | NEONLoadStoreMulti1_3v, 2407 NEON_LD1_4v = NEONLoadStoreMultiStructLoad | NEONLoadStoreMulti1_4v, 2408 NEON_LD2 = NEONLoadStoreMultiStructLoad | NEONLoadStoreMulti2, 2409 NEON_LD3 = NEONLoadStoreMultiStructLoad | NEONLoadStoreMulti3, 2410 NEON_LD4 = NEONLoadStoreMultiStructLoad | NEONLoadStoreMulti4, 2411 NEON_ST1_1v = NEONLoadStoreMultiStructStore | NEONLoadStoreMulti1_1v, 2412 NEON_ST1_2v = NEONLoadStoreMultiStructStore | NEONLoadStoreMulti1_2v, 2413 NEON_ST1_3v = NEONLoadStoreMultiStructStore | NEONLoadStoreMulti1_3v, 2414 NEON_ST1_4v = NEONLoadStoreMultiStructStore | NEONLoadStoreMulti1_4v, 2415 NEON_ST2 = NEONLoadStoreMultiStructStore | NEONLoadStoreMulti2, 2416 NEON_ST3 = NEONLoadStoreMultiStructStore | NEONLoadStoreMulti3, 2417 NEON_ST4 = NEONLoadStoreMultiStructStore | NEONLoadStoreMulti4 2418 }; 2419 2420 // NEON load/store multiple structures with post-index addressing. 2421 enum NEONLoadStoreMultiStructPostIndexOp : uint32_t { 2422 NEONLoadStoreMultiStructPostIndexFixed = 0x0C800000, 2423 NEONLoadStoreMultiStructPostIndexFMask = 0xBFA00000, 2424 NEONLoadStoreMultiStructPostIndexMask = 0xBFE0F000, 2425 NEONLoadStoreMultiStructPostIndex = 0x00800000, 2426 NEON_LD1_1v_post = NEON_LD1_1v | NEONLoadStoreMultiStructPostIndex, 2427 NEON_LD1_2v_post = NEON_LD1_2v | NEONLoadStoreMultiStructPostIndex, 2428 NEON_LD1_3v_post = NEON_LD1_3v | NEONLoadStoreMultiStructPostIndex, 2429 NEON_LD1_4v_post = NEON_LD1_4v | NEONLoadStoreMultiStructPostIndex, 2430 NEON_LD2_post = NEON_LD2 | NEONLoadStoreMultiStructPostIndex, 2431 NEON_LD3_post = NEON_LD3 | NEONLoadStoreMultiStructPostIndex, 2432 NEON_LD4_post = NEON_LD4 | NEONLoadStoreMultiStructPostIndex, 2433 NEON_ST1_1v_post = NEON_ST1_1v | NEONLoadStoreMultiStructPostIndex, 2434 NEON_ST1_2v_post = NEON_ST1_2v | NEONLoadStoreMultiStructPostIndex, 2435 NEON_ST1_3v_post = NEON_ST1_3v | NEONLoadStoreMultiStructPostIndex, 2436 NEON_ST1_4v_post = NEON_ST1_4v | NEONLoadStoreMultiStructPostIndex, 2437 NEON_ST2_post = NEON_ST2 | NEONLoadStoreMultiStructPostIndex, 2438 NEON_ST3_post = NEON_ST3 | NEONLoadStoreMultiStructPostIndex, 2439 NEON_ST4_post = NEON_ST4 | NEONLoadStoreMultiStructPostIndex 2440 }; 2441 2442 enum NEONLoadStoreSingleOp : uint32_t { 2443 NEONLoadStoreSingle1 = 0x00000000, 2444 NEONLoadStoreSingle2 = 0x00200000, 2445 NEONLoadStoreSingle3 = 0x00002000, 2446 NEONLoadStoreSingle4 = 0x00202000, 2447 NEONLoadStoreSingleL = 0x00400000, 2448 NEONLoadStoreSingle_b = 0x00000000, 2449 NEONLoadStoreSingle_h = 0x00004000, 2450 NEONLoadStoreSingle_s = 0x00008000, 2451 NEONLoadStoreSingle_d = 0x00008400, 2452 NEONLoadStoreSingleAllLanes = 0x0000C000, 2453 NEONLoadStoreSingleLenMask = 0x00202000 2454 }; 2455 2456 // NEON load/store single structure. 2457 enum NEONLoadStoreSingleStructOp : uint32_t { 2458 NEONLoadStoreSingleStructFixed = 0x0D000000, 2459 NEONLoadStoreSingleStructFMask = 0xBF9F0000, 2460 NEONLoadStoreSingleStructMask = 0xBFFFE000, 2461 NEONLoadStoreSingleStructStore = NEONLoadStoreSingleStructFixed, 2462 NEONLoadStoreSingleStructLoad = NEONLoadStoreSingleStructFixed | 2463 NEONLoadStoreSingleL, 2464 NEONLoadStoreSingleStructLoad1 = NEONLoadStoreSingle1 | 2465 NEONLoadStoreSingleStructLoad, 2466 NEONLoadStoreSingleStructLoad2 = NEONLoadStoreSingle2 | 2467 NEONLoadStoreSingleStructLoad, 2468 NEONLoadStoreSingleStructLoad3 = NEONLoadStoreSingle3 | 2469 NEONLoadStoreSingleStructLoad, 2470 NEONLoadStoreSingleStructLoad4 = NEONLoadStoreSingle4 | 2471 NEONLoadStoreSingleStructLoad, 2472 NEONLoadStoreSingleStructStore1 = NEONLoadStoreSingle1 | 2473 NEONLoadStoreSingleStructFixed, 2474 NEONLoadStoreSingleStructStore2 = NEONLoadStoreSingle2 | 2475 NEONLoadStoreSingleStructFixed, 2476 NEONLoadStoreSingleStructStore3 = NEONLoadStoreSingle3 | 2477 NEONLoadStoreSingleStructFixed, 2478 NEONLoadStoreSingleStructStore4 = NEONLoadStoreSingle4 | 2479 NEONLoadStoreSingleStructFixed, 2480 NEON_LD1_b = NEONLoadStoreSingleStructLoad1 | NEONLoadStoreSingle_b, 2481 NEON_LD1_h = NEONLoadStoreSingleStructLoad1 | NEONLoadStoreSingle_h, 2482 NEON_LD1_s = NEONLoadStoreSingleStructLoad1 | NEONLoadStoreSingle_s, 2483 NEON_LD1_d = NEONLoadStoreSingleStructLoad1 | NEONLoadStoreSingle_d, 2484 NEON_LD1R = NEONLoadStoreSingleStructLoad1 | NEONLoadStoreSingleAllLanes, 2485 NEON_ST1_b = NEONLoadStoreSingleStructStore1 | NEONLoadStoreSingle_b, 2486 NEON_ST1_h = NEONLoadStoreSingleStructStore1 | NEONLoadStoreSingle_h, 2487 NEON_ST1_s = NEONLoadStoreSingleStructStore1 | NEONLoadStoreSingle_s, 2488 NEON_ST1_d = NEONLoadStoreSingleStructStore1 | NEONLoadStoreSingle_d, 2489 2490 NEON_LD2_b = NEONLoadStoreSingleStructLoad2 | NEONLoadStoreSingle_b, 2491 NEON_LD2_h = NEONLoadStoreSingleStructLoad2 | NEONLoadStoreSingle_h, 2492 NEON_LD2_s = NEONLoadStoreSingleStructLoad2 | NEONLoadStoreSingle_s, 2493 NEON_LD2_d = NEONLoadStoreSingleStructLoad2 | NEONLoadStoreSingle_d, 2494 NEON_LD2R = NEONLoadStoreSingleStructLoad2 | NEONLoadStoreSingleAllLanes, 2495 NEON_ST2_b = NEONLoadStoreSingleStructStore2 | NEONLoadStoreSingle_b, 2496 NEON_ST2_h = NEONLoadStoreSingleStructStore2 | NEONLoadStoreSingle_h, 2497 NEON_ST2_s = NEONLoadStoreSingleStructStore2 | NEONLoadStoreSingle_s, 2498 NEON_ST2_d = NEONLoadStoreSingleStructStore2 | NEONLoadStoreSingle_d, 2499 2500 NEON_LD3_b = NEONLoadStoreSingleStructLoad3 | NEONLoadStoreSingle_b, 2501 NEON_LD3_h = NEONLoadStoreSingleStructLoad3 | NEONLoadStoreSingle_h, 2502 NEON_LD3_s = NEONLoadStoreSingleStructLoad3 | NEONLoadStoreSingle_s, 2503 NEON_LD3_d = NEONLoadStoreSingleStructLoad3 | NEONLoadStoreSingle_d, 2504 NEON_LD3R = NEONLoadStoreSingleStructLoad3 | NEONLoadStoreSingleAllLanes, 2505 NEON_ST3_b = NEONLoadStoreSingleStructStore3 | NEONLoadStoreSingle_b, 2506 NEON_ST3_h = NEONLoadStoreSingleStructStore3 | NEONLoadStoreSingle_h, 2507 NEON_ST3_s = NEONLoadStoreSingleStructStore3 | NEONLoadStoreSingle_s, 2508 NEON_ST3_d = NEONLoadStoreSingleStructStore3 | NEONLoadStoreSingle_d, 2509 2510 NEON_LD4_b = NEONLoadStoreSingleStructLoad4 | NEONLoadStoreSingle_b, 2511 NEON_LD4_h = NEONLoadStoreSingleStructLoad4 | NEONLoadStoreSingle_h, 2512 NEON_LD4_s = NEONLoadStoreSingleStructLoad4 | NEONLoadStoreSingle_s, 2513 NEON_LD4_d = NEONLoadStoreSingleStructLoad4 | NEONLoadStoreSingle_d, 2514 NEON_LD4R = NEONLoadStoreSingleStructLoad4 | NEONLoadStoreSingleAllLanes, 2515 NEON_ST4_b = NEONLoadStoreSingleStructStore4 | NEONLoadStoreSingle_b, 2516 NEON_ST4_h = NEONLoadStoreSingleStructStore4 | NEONLoadStoreSingle_h, 2517 NEON_ST4_s = NEONLoadStoreSingleStructStore4 | NEONLoadStoreSingle_s, 2518 NEON_ST4_d = NEONLoadStoreSingleStructStore4 | NEONLoadStoreSingle_d 2519 }; 2520 2521 // NEON load/store single structure with post-index addressing. 2522 enum NEONLoadStoreSingleStructPostIndexOp : uint32_t { 2523 NEONLoadStoreSingleStructPostIndexFixed = 0x0D800000, 2524 NEONLoadStoreSingleStructPostIndexFMask = 0xBF800000, 2525 NEONLoadStoreSingleStructPostIndexMask = 0xBFE0E000, 2526 NEONLoadStoreSingleStructPostIndex = 0x00800000, 2527 NEON_LD1_b_post = NEON_LD1_b | NEONLoadStoreSingleStructPostIndex, 2528 NEON_LD1_h_post = NEON_LD1_h | NEONLoadStoreSingleStructPostIndex, 2529 NEON_LD1_s_post = NEON_LD1_s | NEONLoadStoreSingleStructPostIndex, 2530 NEON_LD1_d_post = NEON_LD1_d | NEONLoadStoreSingleStructPostIndex, 2531 NEON_LD1R_post = NEON_LD1R | NEONLoadStoreSingleStructPostIndex, 2532 NEON_ST1_b_post = NEON_ST1_b | NEONLoadStoreSingleStructPostIndex, 2533 NEON_ST1_h_post = NEON_ST1_h | NEONLoadStoreSingleStructPostIndex, 2534 NEON_ST1_s_post = NEON_ST1_s | NEONLoadStoreSingleStructPostIndex, 2535 NEON_ST1_d_post = NEON_ST1_d | NEONLoadStoreSingleStructPostIndex, 2536 2537 NEON_LD2_b_post = NEON_LD2_b | NEONLoadStoreSingleStructPostIndex, 2538 NEON_LD2_h_post = NEON_LD2_h | NEONLoadStoreSingleStructPostIndex, 2539 NEON_LD2_s_post = NEON_LD2_s | NEONLoadStoreSingleStructPostIndex, 2540 NEON_LD2_d_post = NEON_LD2_d | NEONLoadStoreSingleStructPostIndex, 2541 NEON_LD2R_post = NEON_LD2R | NEONLoadStoreSingleStructPostIndex, 2542 NEON_ST2_b_post = NEON_ST2_b | NEONLoadStoreSingleStructPostIndex, 2543 NEON_ST2_h_post = NEON_ST2_h | NEONLoadStoreSingleStructPostIndex, 2544 NEON_ST2_s_post = NEON_ST2_s | NEONLoadStoreSingleStructPostIndex, 2545 NEON_ST2_d_post = NEON_ST2_d | NEONLoadStoreSingleStructPostIndex, 2546 2547 NEON_LD3_b_post = NEON_LD3_b | NEONLoadStoreSingleStructPostIndex, 2548 NEON_LD3_h_post = NEON_LD3_h | NEONLoadStoreSingleStructPostIndex, 2549 NEON_LD3_s_post = NEON_LD3_s | NEONLoadStoreSingleStructPostIndex, 2550 NEON_LD3_d_post = NEON_LD3_d | NEONLoadStoreSingleStructPostIndex, 2551 NEON_LD3R_post = NEON_LD3R | NEONLoadStoreSingleStructPostIndex, 2552 NEON_ST3_b_post = NEON_ST3_b | NEONLoadStoreSingleStructPostIndex, 2553 NEON_ST3_h_post = NEON_ST3_h | NEONLoadStoreSingleStructPostIndex, 2554 NEON_ST3_s_post = NEON_ST3_s | NEONLoadStoreSingleStructPostIndex, 2555 NEON_ST3_d_post = NEON_ST3_d | NEONLoadStoreSingleStructPostIndex, 2556 2557 NEON_LD4_b_post = NEON_LD4_b | NEONLoadStoreSingleStructPostIndex, 2558 NEON_LD4_h_post = NEON_LD4_h | NEONLoadStoreSingleStructPostIndex, 2559 NEON_LD4_s_post = NEON_LD4_s | NEONLoadStoreSingleStructPostIndex, 2560 NEON_LD4_d_post = NEON_LD4_d | NEONLoadStoreSingleStructPostIndex, 2561 NEON_LD4R_post = NEON_LD4R | NEONLoadStoreSingleStructPostIndex, 2562 NEON_ST4_b_post = NEON_ST4_b | NEONLoadStoreSingleStructPostIndex, 2563 NEON_ST4_h_post = NEON_ST4_h | NEONLoadStoreSingleStructPostIndex, 2564 NEON_ST4_s_post = NEON_ST4_s | NEONLoadStoreSingleStructPostIndex, 2565 NEON_ST4_d_post = NEON_ST4_d | NEONLoadStoreSingleStructPostIndex 2566 }; 2567 2568 // NEON modified immediate. 2569 enum NEONModifiedImmediateOp : uint32_t { 2570 NEONModifiedImmediateFixed = 0x0F000400, 2571 NEONModifiedImmediateFMask = 0x9FF80400, 2572 NEONModifiedImmediateOpBit = 0x20000000, 2573 NEONModifiedImmediate_FMOV = NEONModifiedImmediateFixed | 0x00000800, 2574 NEONModifiedImmediate_MOVI = NEONModifiedImmediateFixed | 0x00000000, 2575 NEONModifiedImmediate_MVNI = NEONModifiedImmediateFixed | 0x20000000, 2576 NEONModifiedImmediate_ORR = NEONModifiedImmediateFixed | 0x00001000, 2577 NEONModifiedImmediate_BIC = NEONModifiedImmediateFixed | 0x20001000 2578 }; 2579 2580 // NEON shift immediate. 2581 enum NEONShiftImmediateOp : uint32_t { 2582 NEONShiftImmediateFixed = 0x0F000400, 2583 NEONShiftImmediateFMask = 0x9F800400, 2584 NEONShiftImmediateMask = 0xBF80FC00, 2585 NEONShiftImmediateUBit = 0x20000000, 2586 NEON_SHL = NEONShiftImmediateFixed | 0x00005000, 2587 NEON_SSHLL = NEONShiftImmediateFixed | 0x0000A000, 2588 NEON_USHLL = NEONShiftImmediateFixed | 0x2000A000, 2589 NEON_SLI = NEONShiftImmediateFixed | 0x20005000, 2590 NEON_SRI = NEONShiftImmediateFixed | 0x20004000, 2591 NEON_SHRN = NEONShiftImmediateFixed | 0x00008000, 2592 NEON_RSHRN = NEONShiftImmediateFixed | 0x00008800, 2593 NEON_UQSHRN = NEONShiftImmediateFixed | 0x20009000, 2594 NEON_UQRSHRN = NEONShiftImmediateFixed | 0x20009800, 2595 NEON_SQSHRN = NEONShiftImmediateFixed | 0x00009000, 2596 NEON_SQRSHRN = NEONShiftImmediateFixed | 0x00009800, 2597 NEON_SQSHRUN = NEONShiftImmediateFixed | 0x20008000, 2598 NEON_SQRSHRUN = NEONShiftImmediateFixed | 0x20008800, 2599 NEON_SSHR = NEONShiftImmediateFixed | 0x00000000, 2600 NEON_SRSHR = NEONShiftImmediateFixed | 0x00002000, 2601 NEON_USHR = NEONShiftImmediateFixed | 0x20000000, 2602 NEON_URSHR = NEONShiftImmediateFixed | 0x20002000, 2603 NEON_SSRA = NEONShiftImmediateFixed | 0x00001000, 2604 NEON_SRSRA = NEONShiftImmediateFixed | 0x00003000, 2605 NEON_USRA = NEONShiftImmediateFixed | 0x20001000, 2606 NEON_URSRA = NEONShiftImmediateFixed | 0x20003000, 2607 NEON_SQSHLU = NEONShiftImmediateFixed | 0x20006000, 2608 NEON_SCVTF_imm = NEONShiftImmediateFixed | 0x0000E000, 2609 NEON_UCVTF_imm = NEONShiftImmediateFixed | 0x2000E000, 2610 NEON_FCVTZS_imm = NEONShiftImmediateFixed | 0x0000F800, 2611 NEON_FCVTZU_imm = NEONShiftImmediateFixed | 0x2000F800, 2612 NEON_SQSHL_imm = NEONShiftImmediateFixed | 0x00007000, 2613 NEON_UQSHL_imm = NEONShiftImmediateFixed | 0x20007000 2614 }; 2615 2616 // NEON table. 2617 enum NEONTableOp : uint32_t { 2618 NEONTableFixed = 0x0E000000, 2619 NEONTableFMask = 0xBF208C00, 2620 NEONTableExt = 0x00001000, 2621 NEONTableMask = 0xBF20FC00, 2622 NEON_TBL_1v = NEONTableFixed | 0x00000000, 2623 NEON_TBL_2v = NEONTableFixed | 0x00002000, 2624 NEON_TBL_3v = NEONTableFixed | 0x00004000, 2625 NEON_TBL_4v = NEONTableFixed | 0x00006000, 2626 NEON_TBX_1v = NEON_TBL_1v | NEONTableExt, 2627 NEON_TBX_2v = NEON_TBL_2v | NEONTableExt, 2628 NEON_TBX_3v = NEON_TBL_3v | NEONTableExt, 2629 NEON_TBX_4v = NEON_TBL_4v | NEONTableExt 2630 }; 2631 2632 // NEON perm. 2633 enum NEONPermOp : uint32_t { 2634 NEONPermFixed = 0x0E000800, 2635 NEONPermFMask = 0xBF208C00, 2636 NEONPermMask = 0x3F20FC00, 2637 NEON_UZP1 = NEONPermFixed | 0x00001000, 2638 NEON_TRN1 = NEONPermFixed | 0x00002000, 2639 NEON_ZIP1 = NEONPermFixed | 0x00003000, 2640 NEON_UZP2 = NEONPermFixed | 0x00005000, 2641 NEON_TRN2 = NEONPermFixed | 0x00006000, 2642 NEON_ZIP2 = NEONPermFixed | 0x00007000 2643 }; 2644 2645 // NEON scalar instructions with two register operands. 2646 enum NEONScalar2RegMiscOp : uint32_t { 2647 NEONScalar2RegMiscFixed = 0x5E200800, 2648 NEONScalar2RegMiscFMask = 0xDF3E0C00, 2649 NEONScalar2RegMiscMask = NEON_Q | NEONScalar | NEON2RegMiscMask, 2650 NEON_CMGT_zero_scalar = NEON_Q | NEONScalar | NEON_CMGT_zero, 2651 NEON_CMEQ_zero_scalar = NEON_Q | NEONScalar | NEON_CMEQ_zero, 2652 NEON_CMLT_zero_scalar = NEON_Q | NEONScalar | NEON_CMLT_zero, 2653 NEON_CMGE_zero_scalar = NEON_Q | NEONScalar | NEON_CMGE_zero, 2654 NEON_CMLE_zero_scalar = NEON_Q | NEONScalar | NEON_CMLE_zero, 2655 NEON_ABS_scalar = NEON_Q | NEONScalar | NEON_ABS, 2656 NEON_SQABS_scalar = NEON_Q | NEONScalar | NEON_SQABS, 2657 NEON_NEG_scalar = NEON_Q | NEONScalar | NEON_NEG, 2658 NEON_SQNEG_scalar = NEON_Q | NEONScalar | NEON_SQNEG, 2659 NEON_SQXTN_scalar = NEON_Q | NEONScalar | NEON_SQXTN, 2660 NEON_UQXTN_scalar = NEON_Q | NEONScalar | NEON_UQXTN, 2661 NEON_SQXTUN_scalar = NEON_Q | NEONScalar | NEON_SQXTUN, 2662 NEON_SUQADD_scalar = NEON_Q | NEONScalar | NEON_SUQADD, 2663 NEON_USQADD_scalar = NEON_Q | NEONScalar | NEON_USQADD, 2664 2665 NEONScalar2RegMiscOpcode = NEON2RegMiscOpcode, 2666 NEON_NEG_scalar_opcode = NEON_NEG_scalar & NEONScalar2RegMiscOpcode, 2667 2668 NEONScalar2RegMiscFPMask = NEONScalar2RegMiscMask | 0x00800000, 2669 NEON_FRSQRTE_scalar = NEON_Q | NEONScalar | NEON_FRSQRTE, 2670 NEON_FRECPE_scalar = NEON_Q | NEONScalar | NEON_FRECPE, 2671 NEON_SCVTF_scalar = NEON_Q | NEONScalar | NEON_SCVTF, 2672 NEON_UCVTF_scalar = NEON_Q | NEONScalar | NEON_UCVTF, 2673 NEON_FCMGT_zero_scalar = NEON_Q | NEONScalar | NEON_FCMGT_zero, 2674 NEON_FCMEQ_zero_scalar = NEON_Q | NEONScalar | NEON_FCMEQ_zero, 2675 NEON_FCMLT_zero_scalar = NEON_Q | NEONScalar | NEON_FCMLT_zero, 2676 NEON_FCMGE_zero_scalar = NEON_Q | NEONScalar | NEON_FCMGE_zero, 2677 NEON_FCMLE_zero_scalar = NEON_Q | NEONScalar | NEON_FCMLE_zero, 2678 NEON_FRECPX_scalar = NEONScalar2RegMiscFixed | 0x0081F000, 2679 NEON_FCVTNS_scalar = NEON_Q | NEONScalar | NEON_FCVTNS, 2680 NEON_FCVTNU_scalar = NEON_Q | NEONScalar | NEON_FCVTNU, 2681 NEON_FCVTPS_scalar = NEON_Q | NEONScalar | NEON_FCVTPS, 2682 NEON_FCVTPU_scalar = NEON_Q | NEONScalar | NEON_FCVTPU, 2683 NEON_FCVTMS_scalar = NEON_Q | NEONScalar | NEON_FCVTMS, 2684 NEON_FCVTMU_scalar = NEON_Q | NEONScalar | NEON_FCVTMU, 2685 NEON_FCVTZS_scalar = NEON_Q | NEONScalar | NEON_FCVTZS, 2686 NEON_FCVTZU_scalar = NEON_Q | NEONScalar | NEON_FCVTZU, 2687 NEON_FCVTAS_scalar = NEON_Q | NEONScalar | NEON_FCVTAS, 2688 NEON_FCVTAU_scalar = NEON_Q | NEONScalar | NEON_FCVTAU, 2689 NEON_FCVTXN_scalar = NEON_Q | NEONScalar | NEON_FCVTXN 2690 }; 2691 2692 // NEON instructions with two register operands (FP16). 2693 enum NEONScalar2RegMiscFP16Op : uint32_t { 2694 NEONScalar2RegMiscFP16Fixed = 0x5E780800, 2695 NEONScalar2RegMiscFP16FMask = 0xDF7E0C00, 2696 NEONScalar2RegMiscFP16Mask = 0xFFFFFC00, 2697 NEON_FCVTNS_H_scalar = NEON_Q | NEONScalar | NEON_FCVTNS_H, 2698 NEON_FCVTMS_H_scalar = NEON_Q | NEONScalar | NEON_FCVTMS_H, 2699 NEON_FCVTAS_H_scalar = NEON_Q | NEONScalar | NEON_FCVTAS_H, 2700 NEON_SCVTF_H_scalar = NEON_Q | NEONScalar | NEON_SCVTF_H, 2701 NEON_FCMGT_H_zero_scalar = NEON_Q | NEONScalar | NEON_FCMGT_H_zero, 2702 NEON_FCMEQ_H_zero_scalar = NEON_Q | NEONScalar | NEON_FCMEQ_H_zero, 2703 NEON_FCMLT_H_zero_scalar = NEON_Q | NEONScalar | NEON_FCMLT_H_zero, 2704 NEON_FCVTPS_H_scalar = NEON_Q | NEONScalar | NEON_FCVTPS_H, 2705 NEON_FCVTZS_H_scalar = NEON_Q | NEONScalar | NEON_FCVTZS_H, 2706 NEON_FRECPE_H_scalar = NEON_Q | NEONScalar | NEON_FRECPE_H, 2707 NEON_FRECPX_H_scalar = NEONScalar2RegMiscFP16Fixed | 0x0081F000, 2708 NEON_FCVTNU_H_scalar = NEON_Q | NEONScalar | NEON_FCVTNU_H, 2709 NEON_FCVTMU_H_scalar = NEON_Q | NEONScalar | NEON_FCVTMU_H, 2710 NEON_FCVTAU_H_scalar = NEON_Q | NEONScalar | NEON_FCVTAU_H, 2711 NEON_UCVTF_H_scalar = NEON_Q | NEONScalar | NEON_UCVTF_H, 2712 NEON_FCMGE_H_zero_scalar = NEON_Q | NEONScalar | NEON_FCMGE_H_zero, 2713 NEON_FCMLE_H_zero_scalar = NEON_Q | NEONScalar | NEON_FCMLE_H_zero, 2714 NEON_FCVTPU_H_scalar = NEON_Q | NEONScalar | NEON_FCVTPU_H, 2715 NEON_FCVTZU_H_scalar = NEON_Q | NEONScalar | NEON_FCVTZU_H, 2716 NEON_FRSQRTE_H_scalar = NEON_Q | NEONScalar | NEON_FRSQRTE_H 2717 }; 2718 2719 // NEON scalar instructions with three same-type operands. 2720 enum NEONScalar3SameOp : uint32_t { 2721 NEONScalar3SameFixed = 0x5E200400, 2722 NEONScalar3SameFMask = 0xDF200400, 2723 NEONScalar3SameMask = 0xFF20FC00, 2724 NEON_ADD_scalar = NEON_Q | NEONScalar | NEON_ADD, 2725 NEON_CMEQ_scalar = NEON_Q | NEONScalar | NEON_CMEQ, 2726 NEON_CMGE_scalar = NEON_Q | NEONScalar | NEON_CMGE, 2727 NEON_CMGT_scalar = NEON_Q | NEONScalar | NEON_CMGT, 2728 NEON_CMHI_scalar = NEON_Q | NEONScalar | NEON_CMHI, 2729 NEON_CMHS_scalar = NEON_Q | NEONScalar | NEON_CMHS, 2730 NEON_CMTST_scalar = NEON_Q | NEONScalar | NEON_CMTST, 2731 NEON_SUB_scalar = NEON_Q | NEONScalar | NEON_SUB, 2732 NEON_UQADD_scalar = NEON_Q | NEONScalar | NEON_UQADD, 2733 NEON_SQADD_scalar = NEON_Q | NEONScalar | NEON_SQADD, 2734 NEON_UQSUB_scalar = NEON_Q | NEONScalar | NEON_UQSUB, 2735 NEON_SQSUB_scalar = NEON_Q | NEONScalar | NEON_SQSUB, 2736 NEON_USHL_scalar = NEON_Q | NEONScalar | NEON_USHL, 2737 NEON_SSHL_scalar = NEON_Q | NEONScalar | NEON_SSHL, 2738 NEON_UQSHL_scalar = NEON_Q | NEONScalar | NEON_UQSHL, 2739 NEON_SQSHL_scalar = NEON_Q | NEONScalar | NEON_SQSHL, 2740 NEON_URSHL_scalar = NEON_Q | NEONScalar | NEON_URSHL, 2741 NEON_SRSHL_scalar = NEON_Q | NEONScalar | NEON_SRSHL, 2742 NEON_UQRSHL_scalar = NEON_Q | NEONScalar | NEON_UQRSHL, 2743 NEON_SQRSHL_scalar = NEON_Q | NEONScalar | NEON_SQRSHL, 2744 NEON_SQDMULH_scalar = NEON_Q | NEONScalar | NEON_SQDMULH, 2745 NEON_SQRDMULH_scalar = NEON_Q | NEONScalar | NEON_SQRDMULH, 2746 2747 // NEON floating point scalar instructions with three same-type operands. 2748 NEONScalar3SameFPFixed = NEONScalar3SameFixed | 0x0000C000, 2749 NEONScalar3SameFPFMask = NEONScalar3SameFMask | 0x0000C000, 2750 NEONScalar3SameFPMask = NEONScalar3SameMask | 0x00800000, 2751 NEON_FACGE_scalar = NEON_Q | NEONScalar | NEON_FACGE, 2752 NEON_FACGT_scalar = NEON_Q | NEONScalar | NEON_FACGT, 2753 NEON_FCMEQ_scalar = NEON_Q | NEONScalar | NEON_FCMEQ, 2754 NEON_FCMGE_scalar = NEON_Q | NEONScalar | NEON_FCMGE, 2755 NEON_FCMGT_scalar = NEON_Q | NEONScalar | NEON_FCMGT, 2756 NEON_FMULX_scalar = NEON_Q | NEONScalar | NEON_FMULX, 2757 NEON_FRECPS_scalar = NEON_Q | NEONScalar | NEON_FRECPS, 2758 NEON_FRSQRTS_scalar = NEON_Q | NEONScalar | NEON_FRSQRTS, 2759 NEON_FABD_scalar = NEON_Q | NEONScalar | NEON_FABD 2760 }; 2761 2762 // NEON scalar FP16 instructions with three same-type operands. 2763 enum NEONScalar3SameFP16Op { 2764 NEONScalar3SameFP16Fixed = 0x5E400400, 2765 NEONScalar3SameFP16FMask = 0xDF60C400, 2766 NEONScalar3SameFP16Mask = 0xFFE0FC00, 2767 NEON_FABD_H_scalar = NEON_Q | NEONScalar | NEON_FABD_H, 2768 NEON_FMULX_H_scalar = NEON_Q | NEONScalar | NEON_FMULX_H, 2769 NEON_FCMEQ_H_scalar = NEON_Q | NEONScalar | NEON_FCMEQ_H, 2770 NEON_FCMGE_H_scalar = NEON_Q | NEONScalar | NEON_FCMGE_H, 2771 NEON_FCMGT_H_scalar = NEON_Q | NEONScalar | NEON_FCMGT_H, 2772 NEON_FACGE_H_scalar = NEON_Q | NEONScalar | NEON_FACGE_H, 2773 NEON_FACGT_H_scalar = NEON_Q | NEONScalar | NEON_FACGT_H, 2774 NEON_FRECPS_H_scalar = NEON_Q | NEONScalar | NEON_FRECPS_H, 2775 NEON_FRSQRTS_H_scalar = NEON_Q | NEONScalar | NEON_FRSQRTS_H 2776 }; 2777 2778 // 'Extra' NEON scalar instructions with three same-type operands. 2779 enum NEONScalar3SameExtraOp { 2780 NEONScalar3SameExtraFixed = 0x5E008400, 2781 NEONScalar3SameExtraFMask = 0xDF208400, 2782 NEONScalar3SameExtraMask = 0xFF20FC00, 2783 NEON_SQRDMLAH_scalar = NEON_Q | NEONScalar | NEON_SQRDMLAH, 2784 NEON_SQRDMLSH_scalar = NEON_Q | NEONScalar | NEON_SQRDMLSH 2785 }; 2786 2787 // NEON scalar instructions with three different-type operands. 2788 enum NEONScalar3DiffOp : uint32_t { 2789 NEONScalar3DiffFixed = 0x5E200000, 2790 NEONScalar3DiffFMask = 0xDF200C00, 2791 NEONScalar3DiffMask = NEON_Q | NEONScalar | NEON3DifferentMask, 2792 NEON_SQDMLAL_scalar = NEON_Q | NEONScalar | NEON_SQDMLAL, 2793 NEON_SQDMLSL_scalar = NEON_Q | NEONScalar | NEON_SQDMLSL, 2794 NEON_SQDMULL_scalar = NEON_Q | NEONScalar | NEON_SQDMULL 2795 }; 2796 2797 // NEON scalar instructions with indexed element operand. 2798 enum NEONScalarByIndexedElementOp : uint32_t { 2799 NEONScalarByIndexedElementFixed = 0x5F000000, 2800 NEONScalarByIndexedElementFMask = 0xDF000400, 2801 NEONScalarByIndexedElementMask = 0xFF00F400, 2802 NEON_SQDMLAL_byelement_scalar = NEON_Q | NEONScalar | NEON_SQDMLAL_byelement, 2803 NEON_SQDMLSL_byelement_scalar = NEON_Q | NEONScalar | NEON_SQDMLSL_byelement, 2804 NEON_SQDMULL_byelement_scalar = NEON_Q | NEONScalar | NEON_SQDMULL_byelement, 2805 NEON_SQDMULH_byelement_scalar = NEON_Q | NEONScalar | NEON_SQDMULH_byelement, 2806 NEON_SQRDMULH_byelement_scalar 2807 = NEON_Q | NEONScalar | NEON_SQRDMULH_byelement, 2808 NEON_SQRDMLAH_byelement_scalar 2809 = NEON_Q | NEONScalar | NEON_SQRDMLAH_byelement, 2810 NEON_SQRDMLSH_byelement_scalar 2811 = NEON_Q | NEONScalar | NEON_SQRDMLSH_byelement, 2812 NEON_FMLA_H_byelement_scalar = NEON_Q | NEONScalar | NEON_FMLA_H_byelement, 2813 NEON_FMLS_H_byelement_scalar = NEON_Q | NEONScalar | NEON_FMLS_H_byelement, 2814 NEON_FMUL_H_byelement_scalar = NEON_Q | NEONScalar | NEON_FMUL_H_byelement, 2815 NEON_FMULX_H_byelement_scalar = NEON_Q | NEONScalar | NEON_FMULX_H_byelement, 2816 2817 // Floating point instructions. 2818 NEONScalarByIndexedElementFPFixed 2819 = NEONScalarByIndexedElementFixed | 0x00800000, 2820 NEONScalarByIndexedElementFPMask 2821 = NEONScalarByIndexedElementMask | 0x00800000, 2822 NEON_FMLA_byelement_scalar = NEON_Q | NEONScalar | NEON_FMLA_byelement, 2823 NEON_FMLS_byelement_scalar = NEON_Q | NEONScalar | NEON_FMLS_byelement, 2824 NEON_FMUL_byelement_scalar = NEON_Q | NEONScalar | NEON_FMUL_byelement, 2825 NEON_FMULX_byelement_scalar = NEON_Q | NEONScalar | NEON_FMULX_byelement 2826 }; 2827 2828 // NEON scalar register copy. 2829 enum NEONScalarCopyOp : uint32_t { 2830 NEONScalarCopyFixed = 0x5E000400, 2831 NEONScalarCopyFMask = 0xDFE08400, 2832 NEONScalarCopyMask = 0xFFE0FC00, 2833 NEON_DUP_ELEMENT_scalar = NEON_Q | NEONScalar | NEON_DUP_ELEMENT 2834 }; 2835 2836 // NEON scalar pairwise instructions. 2837 enum NEONScalarPairwiseOp : uint32_t { 2838 NEONScalarPairwiseFixed = 0x5E300800, 2839 NEONScalarPairwiseFMask = 0xDF3E0C00, 2840 NEONScalarPairwiseMask = 0xFFB1F800, 2841 NEON_ADDP_scalar = NEONScalarPairwiseFixed | 0x0081B000, 2842 NEON_FMAXNMP_h_scalar = NEONScalarPairwiseFixed | 0x0000C000, 2843 NEON_FADDP_h_scalar = NEONScalarPairwiseFixed | 0x0000D000, 2844 NEON_FMAXP_h_scalar = NEONScalarPairwiseFixed | 0x0000F000, 2845 NEON_FMINNMP_h_scalar = NEONScalarPairwiseFixed | 0x0080C000, 2846 NEON_FMINP_h_scalar = NEONScalarPairwiseFixed | 0x0080F000, 2847 NEON_FMAXNMP_scalar = NEONScalarPairwiseFixed | 0x2000C000, 2848 NEON_FMINNMP_scalar = NEONScalarPairwiseFixed | 0x2080C000, 2849 NEON_FADDP_scalar = NEONScalarPairwiseFixed | 0x2000D000, 2850 NEON_FMAXP_scalar = NEONScalarPairwiseFixed | 0x2000F000, 2851 NEON_FMINP_scalar = NEONScalarPairwiseFixed | 0x2080F000 2852 }; 2853 2854 // NEON scalar shift immediate. 2855 enum NEONScalarShiftImmediateOp : uint32_t { 2856 NEONScalarShiftImmediateFixed = 0x5F000400, 2857 NEONScalarShiftImmediateFMask = 0xDF800400, 2858 NEONScalarShiftImmediateMask = 0xFF80FC00, 2859 NEON_SHL_scalar = NEON_Q | NEONScalar | NEON_SHL, 2860 NEON_SLI_scalar = NEON_Q | NEONScalar | NEON_SLI, 2861 NEON_SRI_scalar = NEON_Q | NEONScalar | NEON_SRI, 2862 NEON_SSHR_scalar = NEON_Q | NEONScalar | NEON_SSHR, 2863 NEON_USHR_scalar = NEON_Q | NEONScalar | NEON_USHR, 2864 NEON_SRSHR_scalar = NEON_Q | NEONScalar | NEON_SRSHR, 2865 NEON_URSHR_scalar = NEON_Q | NEONScalar | NEON_URSHR, 2866 NEON_SSRA_scalar = NEON_Q | NEONScalar | NEON_SSRA, 2867 NEON_USRA_scalar = NEON_Q | NEONScalar | NEON_USRA, 2868 NEON_SRSRA_scalar = NEON_Q | NEONScalar | NEON_SRSRA, 2869 NEON_URSRA_scalar = NEON_Q | NEONScalar | NEON_URSRA, 2870 NEON_UQSHRN_scalar = NEON_Q | NEONScalar | NEON_UQSHRN, 2871 NEON_UQRSHRN_scalar = NEON_Q | NEONScalar | NEON_UQRSHRN, 2872 NEON_SQSHRN_scalar = NEON_Q | NEONScalar | NEON_SQSHRN, 2873 NEON_SQRSHRN_scalar = NEON_Q | NEONScalar | NEON_SQRSHRN, 2874 NEON_SQSHRUN_scalar = NEON_Q | NEONScalar | NEON_SQSHRUN, 2875 NEON_SQRSHRUN_scalar = NEON_Q | NEONScalar | NEON_SQRSHRUN, 2876 NEON_SQSHLU_scalar = NEON_Q | NEONScalar | NEON_SQSHLU, 2877 NEON_SQSHL_imm_scalar = NEON_Q | NEONScalar | NEON_SQSHL_imm, 2878 NEON_UQSHL_imm_scalar = NEON_Q | NEONScalar | NEON_UQSHL_imm, 2879 NEON_SCVTF_imm_scalar = NEON_Q | NEONScalar | NEON_SCVTF_imm, 2880 NEON_UCVTF_imm_scalar = NEON_Q | NEONScalar | NEON_UCVTF_imm, 2881 NEON_FCVTZS_imm_scalar = NEON_Q | NEONScalar | NEON_FCVTZS_imm, 2882 NEON_FCVTZU_imm_scalar = NEON_Q | NEONScalar | NEON_FCVTZU_imm 2883 }; 2884 2885 enum SVE32BitGatherLoadHalfwords_ScalarPlus32BitScaledOffsetsOp { 2886 SVE32BitGatherLoadHalfwords_ScalarPlus32BitScaledOffsetsFixed = 0x84A00000, 2887 SVE32BitGatherLoadHalfwords_ScalarPlus32BitScaledOffsetsFMask = 0xFFA08000, 2888 SVE32BitGatherLoadHalfwords_ScalarPlus32BitScaledOffsetsMask = 0xFFA0E000, 2889 LD1SH_z_p_bz_s_x32_scaled = SVE32BitGatherLoadHalfwords_ScalarPlus32BitScaledOffsetsFixed, 2890 LDFF1SH_z_p_bz_s_x32_scaled = SVE32BitGatherLoadHalfwords_ScalarPlus32BitScaledOffsetsFixed | 0x00002000, 2891 LD1H_z_p_bz_s_x32_scaled = SVE32BitGatherLoadHalfwords_ScalarPlus32BitScaledOffsetsFixed | 0x00004000, 2892 LDFF1H_z_p_bz_s_x32_scaled = SVE32BitGatherLoadHalfwords_ScalarPlus32BitScaledOffsetsFixed | 0x00006000 2893 }; 2894 2895 enum SVE32BitGatherLoadWords_ScalarPlus32BitScaledOffsetsOp { 2896 SVE32BitGatherLoadWords_ScalarPlus32BitScaledOffsetsFixed = 0x85200000, 2897 SVE32BitGatherLoadWords_ScalarPlus32BitScaledOffsetsFMask = 0xFFA08000, 2898 SVE32BitGatherLoadWords_ScalarPlus32BitScaledOffsetsMask = 0xFFA0E000, 2899 LD1W_z_p_bz_s_x32_scaled = SVE32BitGatherLoadWords_ScalarPlus32BitScaledOffsetsFixed | 0x00004000, 2900 LDFF1W_z_p_bz_s_x32_scaled = SVE32BitGatherLoadWords_ScalarPlus32BitScaledOffsetsFixed | 0x00006000 2901 }; 2902 2903 enum SVE32BitGatherLoad_ScalarPlus32BitUnscaledOffsetsOp { 2904 SVE32BitGatherLoad_ScalarPlus32BitUnscaledOffsetsFixed = 0x84000000, 2905 SVE32BitGatherLoad_ScalarPlus32BitUnscaledOffsetsFMask = 0xFE208000, 2906 SVE32BitGatherLoad_ScalarPlus32BitUnscaledOffsetsMask = 0xFFA0E000, 2907 LD1SB_z_p_bz_s_x32_unscaled = SVE32BitGatherLoad_ScalarPlus32BitUnscaledOffsetsFixed, 2908 LDFF1SB_z_p_bz_s_x32_unscaled = SVE32BitGatherLoad_ScalarPlus32BitUnscaledOffsetsFixed | 0x00002000, 2909 LD1B_z_p_bz_s_x32_unscaled = SVE32BitGatherLoad_ScalarPlus32BitUnscaledOffsetsFixed | 0x00004000, 2910 LDFF1B_z_p_bz_s_x32_unscaled = SVE32BitGatherLoad_ScalarPlus32BitUnscaledOffsetsFixed | 0x00006000, 2911 LD1SH_z_p_bz_s_x32_unscaled = SVE32BitGatherLoad_ScalarPlus32BitUnscaledOffsetsFixed | 0x00800000, 2912 LDFF1SH_z_p_bz_s_x32_unscaled = SVE32BitGatherLoad_ScalarPlus32BitUnscaledOffsetsFixed | 0x00802000, 2913 LD1H_z_p_bz_s_x32_unscaled = SVE32BitGatherLoad_ScalarPlus32BitUnscaledOffsetsFixed | 0x00804000, 2914 LDFF1H_z_p_bz_s_x32_unscaled = SVE32BitGatherLoad_ScalarPlus32BitUnscaledOffsetsFixed | 0x00806000, 2915 LD1W_z_p_bz_s_x32_unscaled = SVE32BitGatherLoad_ScalarPlus32BitUnscaledOffsetsFixed | 0x01004000, 2916 LDFF1W_z_p_bz_s_x32_unscaled = SVE32BitGatherLoad_ScalarPlus32BitUnscaledOffsetsFixed | 0x01006000 2917 }; 2918 2919 enum SVE32BitGatherLoad_VectorPlusImmOp { 2920 SVE32BitGatherLoad_VectorPlusImmFixed = 0x84208000, 2921 SVE32BitGatherLoad_VectorPlusImmFMask = 0xFE608000, 2922 SVE32BitGatherLoad_VectorPlusImmMask = 0xFFE0E000, 2923 LD1SB_z_p_ai_s = SVE32BitGatherLoad_VectorPlusImmFixed, 2924 LDFF1SB_z_p_ai_s = SVE32BitGatherLoad_VectorPlusImmFixed | 0x00002000, 2925 LD1B_z_p_ai_s = SVE32BitGatherLoad_VectorPlusImmFixed | 0x00004000, 2926 LDFF1B_z_p_ai_s = SVE32BitGatherLoad_VectorPlusImmFixed | 0x00006000, 2927 LD1SH_z_p_ai_s = SVE32BitGatherLoad_VectorPlusImmFixed | 0x00800000, 2928 LDFF1SH_z_p_ai_s = SVE32BitGatherLoad_VectorPlusImmFixed | 0x00802000, 2929 LD1H_z_p_ai_s = SVE32BitGatherLoad_VectorPlusImmFixed | 0x00804000, 2930 LDFF1H_z_p_ai_s = SVE32BitGatherLoad_VectorPlusImmFixed | 0x00806000, 2931 LD1W_z_p_ai_s = SVE32BitGatherLoad_VectorPlusImmFixed | 0x01004000, 2932 LDFF1W_z_p_ai_s = SVE32BitGatherLoad_VectorPlusImmFixed | 0x01006000 2933 }; 2934 2935 enum SVE32BitGatherPrefetch_ScalarPlus32BitScaledOffsetsOp { 2936 SVE32BitGatherPrefetch_ScalarPlus32BitScaledOffsetsFixed = 0x84200000, 2937 SVE32BitGatherPrefetch_ScalarPlus32BitScaledOffsetsFMask = 0xFFA08010, 2938 SVE32BitGatherPrefetch_ScalarPlus32BitScaledOffsetsMask = 0xFFA0E010, 2939 PRFB_i_p_bz_s_x32_scaled = SVE32BitGatherPrefetch_ScalarPlus32BitScaledOffsetsFixed, 2940 PRFH_i_p_bz_s_x32_scaled = SVE32BitGatherPrefetch_ScalarPlus32BitScaledOffsetsFixed | 0x00002000, 2941 PRFW_i_p_bz_s_x32_scaled = SVE32BitGatherPrefetch_ScalarPlus32BitScaledOffsetsFixed | 0x00004000, 2942 PRFD_i_p_bz_s_x32_scaled = SVE32BitGatherPrefetch_ScalarPlus32BitScaledOffsetsFixed | 0x00006000 2943 }; 2944 2945 enum SVE32BitGatherPrefetch_VectorPlusImmOp { 2946 SVE32BitGatherPrefetch_VectorPlusImmFixed = 0x8400E000, 2947 SVE32BitGatherPrefetch_VectorPlusImmFMask = 0xFE60E010, 2948 SVE32BitGatherPrefetch_VectorPlusImmMask = 0xFFE0E010, 2949 PRFB_i_p_ai_s = SVE32BitGatherPrefetch_VectorPlusImmFixed, 2950 PRFH_i_p_ai_s = SVE32BitGatherPrefetch_VectorPlusImmFixed | 0x00800000, 2951 PRFW_i_p_ai_s = SVE32BitGatherPrefetch_VectorPlusImmFixed | 0x01000000, 2952 PRFD_i_p_ai_s = SVE32BitGatherPrefetch_VectorPlusImmFixed | 0x01800000 2953 }; 2954 2955 enum SVE32BitScatterStore_ScalarPlus32BitScaledOffsetsOp { 2956 SVE32BitScatterStore_ScalarPlus32BitScaledOffsetsFixed = 0xE4608000, 2957 SVE32BitScatterStore_ScalarPlus32BitScaledOffsetsFMask = 0xFE60A000, 2958 SVE32BitScatterStore_ScalarPlus32BitScaledOffsetsMask = 0xFFE0A000, 2959 ST1H_z_p_bz_s_x32_scaled = SVE32BitScatterStore_ScalarPlus32BitScaledOffsetsFixed | 0x00800000, 2960 ST1W_z_p_bz_s_x32_scaled = SVE32BitScatterStore_ScalarPlus32BitScaledOffsetsFixed | 0x01000000 2961 }; 2962 2963 enum SVE32BitScatterStore_ScalarPlus32BitUnscaledOffsetsOp { 2964 SVE32BitScatterStore_ScalarPlus32BitUnscaledOffsetsFixed = 0xE4408000, 2965 SVE32BitScatterStore_ScalarPlus32BitUnscaledOffsetsFMask = 0xFE60A000, 2966 SVE32BitScatterStore_ScalarPlus32BitUnscaledOffsetsMask = 0xFFE0A000, 2967 ST1B_z_p_bz_s_x32_unscaled = SVE32BitScatterStore_ScalarPlus32BitUnscaledOffsetsFixed, 2968 ST1H_z_p_bz_s_x32_unscaled = SVE32BitScatterStore_ScalarPlus32BitUnscaledOffsetsFixed | 0x00800000, 2969 ST1W_z_p_bz_s_x32_unscaled = SVE32BitScatterStore_ScalarPlus32BitUnscaledOffsetsFixed | 0x01000000 2970 }; 2971 2972 enum SVE32BitScatterStore_VectorPlusImmOp { 2973 SVE32BitScatterStore_VectorPlusImmFixed = 0xE460A000, 2974 SVE32BitScatterStore_VectorPlusImmFMask = 0xFE60E000, 2975 SVE32BitScatterStore_VectorPlusImmMask = 0xFFE0E000, 2976 ST1B_z_p_ai_s = SVE32BitScatterStore_VectorPlusImmFixed, 2977 ST1H_z_p_ai_s = SVE32BitScatterStore_VectorPlusImmFixed | 0x00800000, 2978 ST1W_z_p_ai_s = SVE32BitScatterStore_VectorPlusImmFixed | 0x01000000 2979 }; 2980 2981 enum SVE64BitGatherLoad_ScalarPlus32BitUnpackedScaledOffsetsOp { 2982 SVE64BitGatherLoad_ScalarPlus32BitUnpackedScaledOffsetsFixed = 0xC4200000, 2983 SVE64BitGatherLoad_ScalarPlus32BitUnpackedScaledOffsetsFMask = 0xFE208000, 2984 SVE64BitGatherLoad_ScalarPlus32BitUnpackedScaledOffsetsMask = 0xFFA0E000, 2985 LD1SH_z_p_bz_d_x32_scaled = SVE64BitGatherLoad_ScalarPlus32BitUnpackedScaledOffsetsFixed | 0x00800000, 2986 LDFF1SH_z_p_bz_d_x32_scaled = SVE64BitGatherLoad_ScalarPlus32BitUnpackedScaledOffsetsFixed | 0x00802000, 2987 LD1H_z_p_bz_d_x32_scaled = SVE64BitGatherLoad_ScalarPlus32BitUnpackedScaledOffsetsFixed | 0x00804000, 2988 LDFF1H_z_p_bz_d_x32_scaled = SVE64BitGatherLoad_ScalarPlus32BitUnpackedScaledOffsetsFixed | 0x00806000, 2989 LD1SW_z_p_bz_d_x32_scaled = SVE64BitGatherLoad_ScalarPlus32BitUnpackedScaledOffsetsFixed | 0x01000000, 2990 LDFF1SW_z_p_bz_d_x32_scaled = SVE64BitGatherLoad_ScalarPlus32BitUnpackedScaledOffsetsFixed | 0x01002000, 2991 LD1W_z_p_bz_d_x32_scaled = SVE64BitGatherLoad_ScalarPlus32BitUnpackedScaledOffsetsFixed | 0x01004000, 2992 LDFF1W_z_p_bz_d_x32_scaled = SVE64BitGatherLoad_ScalarPlus32BitUnpackedScaledOffsetsFixed | 0x01006000, 2993 LD1D_z_p_bz_d_x32_scaled = SVE64BitGatherLoad_ScalarPlus32BitUnpackedScaledOffsetsFixed | 0x01804000, 2994 LDFF1D_z_p_bz_d_x32_scaled = SVE64BitGatherLoad_ScalarPlus32BitUnpackedScaledOffsetsFixed | 0x01806000 2995 }; 2996 2997 enum SVE64BitGatherLoad_ScalarPlus64BitScaledOffsetsOp { 2998 SVE64BitGatherLoad_ScalarPlus64BitScaledOffsetsFixed = 0xC4608000, 2999 SVE64BitGatherLoad_ScalarPlus64BitScaledOffsetsFMask = 0xFE608000, 3000 SVE64BitGatherLoad_ScalarPlus64BitScaledOffsetsMask = 0xFFE0E000, 3001 LD1SH_z_p_bz_d_64_scaled = SVE64BitGatherLoad_ScalarPlus64BitScaledOffsetsFixed | 0x00800000, 3002 LDFF1SH_z_p_bz_d_64_scaled = SVE64BitGatherLoad_ScalarPlus64BitScaledOffsetsFixed | 0x00802000, 3003 LD1H_z_p_bz_d_64_scaled = SVE64BitGatherLoad_ScalarPlus64BitScaledOffsetsFixed | 0x00804000, 3004 LDFF1H_z_p_bz_d_64_scaled = SVE64BitGatherLoad_ScalarPlus64BitScaledOffsetsFixed | 0x00806000, 3005 LD1SW_z_p_bz_d_64_scaled = SVE64BitGatherLoad_ScalarPlus64BitScaledOffsetsFixed | 0x01000000, 3006 LDFF1SW_z_p_bz_d_64_scaled = SVE64BitGatherLoad_ScalarPlus64BitScaledOffsetsFixed | 0x01002000, 3007 LD1W_z_p_bz_d_64_scaled = SVE64BitGatherLoad_ScalarPlus64BitScaledOffsetsFixed | 0x01004000, 3008 LDFF1W_z_p_bz_d_64_scaled = SVE64BitGatherLoad_ScalarPlus64BitScaledOffsetsFixed | 0x01006000, 3009 LD1D_z_p_bz_d_64_scaled = SVE64BitGatherLoad_ScalarPlus64BitScaledOffsetsFixed | 0x01804000, 3010 LDFF1D_z_p_bz_d_64_scaled = SVE64BitGatherLoad_ScalarPlus64BitScaledOffsetsFixed | 0x01806000 3011 }; 3012 3013 enum SVE64BitGatherLoad_ScalarPlus64BitUnscaledOffsetsOp { 3014 SVE64BitGatherLoad_ScalarPlus64BitUnscaledOffsetsFixed = 0xC4408000, 3015 SVE64BitGatherLoad_ScalarPlus64BitUnscaledOffsetsFMask = 0xFE608000, 3016 SVE64BitGatherLoad_ScalarPlus64BitUnscaledOffsetsMask = 0xFFE0E000, 3017 LD1SB_z_p_bz_d_64_unscaled = SVE64BitGatherLoad_ScalarPlus64BitUnscaledOffsetsFixed, 3018 LDFF1SB_z_p_bz_d_64_unscaled = SVE64BitGatherLoad_ScalarPlus64BitUnscaledOffsetsFixed | 0x00002000, 3019 LD1B_z_p_bz_d_64_unscaled = SVE64BitGatherLoad_ScalarPlus64BitUnscaledOffsetsFixed | 0x00004000, 3020 LDFF1B_z_p_bz_d_64_unscaled = SVE64BitGatherLoad_ScalarPlus64BitUnscaledOffsetsFixed | 0x00006000, 3021 LD1SH_z_p_bz_d_64_unscaled = SVE64BitGatherLoad_ScalarPlus64BitUnscaledOffsetsFixed | 0x00800000, 3022 LDFF1SH_z_p_bz_d_64_unscaled = SVE64BitGatherLoad_ScalarPlus64BitUnscaledOffsetsFixed | 0x00802000, 3023 LD1H_z_p_bz_d_64_unscaled = SVE64BitGatherLoad_ScalarPlus64BitUnscaledOffsetsFixed | 0x00804000, 3024 LDFF1H_z_p_bz_d_64_unscaled = SVE64BitGatherLoad_ScalarPlus64BitUnscaledOffsetsFixed | 0x00806000, 3025 LD1SW_z_p_bz_d_64_unscaled = SVE64BitGatherLoad_ScalarPlus64BitUnscaledOffsetsFixed | 0x01000000, 3026 LDFF1SW_z_p_bz_d_64_unscaled = SVE64BitGatherLoad_ScalarPlus64BitUnscaledOffsetsFixed | 0x01002000, 3027 LD1W_z_p_bz_d_64_unscaled = SVE64BitGatherLoad_ScalarPlus64BitUnscaledOffsetsFixed | 0x01004000, 3028 LDFF1W_z_p_bz_d_64_unscaled = SVE64BitGatherLoad_ScalarPlus64BitUnscaledOffsetsFixed | 0x01006000, 3029 LD1D_z_p_bz_d_64_unscaled = SVE64BitGatherLoad_ScalarPlus64BitUnscaledOffsetsFixed | 0x01804000, 3030 LDFF1D_z_p_bz_d_64_unscaled = SVE64BitGatherLoad_ScalarPlus64BitUnscaledOffsetsFixed | 0x01806000 3031 }; 3032 3033 enum SVE64BitGatherLoad_ScalarPlusUnpacked32BitUnscaledOffsetsOp { 3034 SVE64BitGatherLoad_ScalarPlusUnpacked32BitUnscaledOffsetsFixed = 0xC4000000, 3035 SVE64BitGatherLoad_ScalarPlusUnpacked32BitUnscaledOffsetsFMask = 0xFE208000, 3036 SVE64BitGatherLoad_ScalarPlusUnpacked32BitUnscaledOffsetsMask = 0xFFA0E000, 3037 LD1SB_z_p_bz_d_x32_unscaled = SVE64BitGatherLoad_ScalarPlusUnpacked32BitUnscaledOffsetsFixed, 3038 LDFF1SB_z_p_bz_d_x32_unscaled = SVE64BitGatherLoad_ScalarPlusUnpacked32BitUnscaledOffsetsFixed | 0x00002000, 3039 LD1B_z_p_bz_d_x32_unscaled = SVE64BitGatherLoad_ScalarPlusUnpacked32BitUnscaledOffsetsFixed | 0x00004000, 3040 LDFF1B_z_p_bz_d_x32_unscaled = SVE64BitGatherLoad_ScalarPlusUnpacked32BitUnscaledOffsetsFixed | 0x00006000, 3041 LD1SH_z_p_bz_d_x32_unscaled = SVE64BitGatherLoad_ScalarPlusUnpacked32BitUnscaledOffsetsFixed | 0x00800000, 3042 LDFF1SH_z_p_bz_d_x32_unscaled = SVE64BitGatherLoad_ScalarPlusUnpacked32BitUnscaledOffsetsFixed | 0x00802000, 3043 LD1H_z_p_bz_d_x32_unscaled = SVE64BitGatherLoad_ScalarPlusUnpacked32BitUnscaledOffsetsFixed | 0x00804000, 3044 LDFF1H_z_p_bz_d_x32_unscaled = SVE64BitGatherLoad_ScalarPlusUnpacked32BitUnscaledOffsetsFixed | 0x00806000, 3045 LD1SW_z_p_bz_d_x32_unscaled = SVE64BitGatherLoad_ScalarPlusUnpacked32BitUnscaledOffsetsFixed | 0x01000000, 3046 LDFF1SW_z_p_bz_d_x32_unscaled = SVE64BitGatherLoad_ScalarPlusUnpacked32BitUnscaledOffsetsFixed | 0x01002000, 3047 LD1W_z_p_bz_d_x32_unscaled = SVE64BitGatherLoad_ScalarPlusUnpacked32BitUnscaledOffsetsFixed | 0x01004000, 3048 LDFF1W_z_p_bz_d_x32_unscaled = SVE64BitGatherLoad_ScalarPlusUnpacked32BitUnscaledOffsetsFixed | 0x01006000, 3049 LD1D_z_p_bz_d_x32_unscaled = SVE64BitGatherLoad_ScalarPlusUnpacked32BitUnscaledOffsetsFixed | 0x01804000, 3050 LDFF1D_z_p_bz_d_x32_unscaled = SVE64BitGatherLoad_ScalarPlusUnpacked32BitUnscaledOffsetsFixed | 0x01806000 3051 }; 3052 3053 enum SVE64BitGatherLoad_VectorPlusImmOp { 3054 SVE64BitGatherLoad_VectorPlusImmFixed = 0xC4208000, 3055 SVE64BitGatherLoad_VectorPlusImmFMask = 0xFE608000, 3056 SVE64BitGatherLoad_VectorPlusImmMask = 0xFFE0E000, 3057 LD1SB_z_p_ai_d = SVE64BitGatherLoad_VectorPlusImmFixed, 3058 LDFF1SB_z_p_ai_d = SVE64BitGatherLoad_VectorPlusImmFixed | 0x00002000, 3059 LD1B_z_p_ai_d = SVE64BitGatherLoad_VectorPlusImmFixed | 0x00004000, 3060 LDFF1B_z_p_ai_d = SVE64BitGatherLoad_VectorPlusImmFixed | 0x00006000, 3061 LD1SH_z_p_ai_d = SVE64BitGatherLoad_VectorPlusImmFixed | 0x00800000, 3062 LDFF1SH_z_p_ai_d = SVE64BitGatherLoad_VectorPlusImmFixed | 0x00802000, 3063 LD1H_z_p_ai_d = SVE64BitGatherLoad_VectorPlusImmFixed | 0x00804000, 3064 LDFF1H_z_p_ai_d = SVE64BitGatherLoad_VectorPlusImmFixed | 0x00806000, 3065 LD1SW_z_p_ai_d = SVE64BitGatherLoad_VectorPlusImmFixed | 0x01000000, 3066 LDFF1SW_z_p_ai_d = SVE64BitGatherLoad_VectorPlusImmFixed | 0x01002000, 3067 LD1W_z_p_ai_d = SVE64BitGatherLoad_VectorPlusImmFixed | 0x01004000, 3068 LDFF1W_z_p_ai_d = SVE64BitGatherLoad_VectorPlusImmFixed | 0x01006000, 3069 LD1D_z_p_ai_d = SVE64BitGatherLoad_VectorPlusImmFixed | 0x01804000, 3070 LDFF1D_z_p_ai_d = SVE64BitGatherLoad_VectorPlusImmFixed | 0x01806000 3071 }; 3072 3073 enum SVE64BitGatherPrefetch_ScalarPlus64BitScaledOffsetsOp { 3074 SVE64BitGatherPrefetch_ScalarPlus64BitScaledOffsetsFixed = 0xC4608000, 3075 SVE64BitGatherPrefetch_ScalarPlus64BitScaledOffsetsFMask = 0xFFE08010, 3076 SVE64BitGatherPrefetch_ScalarPlus64BitScaledOffsetsMask = 0xFFE0E010, 3077 PRFB_i_p_bz_d_64_scaled = SVE64BitGatherPrefetch_ScalarPlus64BitScaledOffsetsFixed, 3078 PRFH_i_p_bz_d_64_scaled = SVE64BitGatherPrefetch_ScalarPlus64BitScaledOffsetsFixed | 0x00002000, 3079 PRFW_i_p_bz_d_64_scaled = SVE64BitGatherPrefetch_ScalarPlus64BitScaledOffsetsFixed | 0x00004000, 3080 PRFD_i_p_bz_d_64_scaled = SVE64BitGatherPrefetch_ScalarPlus64BitScaledOffsetsFixed | 0x00006000 3081 }; 3082 3083 enum SVE64BitGatherPrefetch_ScalarPlusUnpacked32BitScaledOffsetsOp { 3084 SVE64BitGatherPrefetch_ScalarPlusUnpacked32BitScaledOffsetsFixed = 0xC4200000, 3085 SVE64BitGatherPrefetch_ScalarPlusUnpacked32BitScaledOffsetsFMask = 0xFFA08010, 3086 SVE64BitGatherPrefetch_ScalarPlusUnpacked32BitScaledOffsetsMask = 0xFFA0E010, 3087 PRFB_i_p_bz_d_x32_scaled = SVE64BitGatherPrefetch_ScalarPlusUnpacked32BitScaledOffsetsFixed, 3088 PRFH_i_p_bz_d_x32_scaled = SVE64BitGatherPrefetch_ScalarPlusUnpacked32BitScaledOffsetsFixed | 0x00002000, 3089 PRFW_i_p_bz_d_x32_scaled = SVE64BitGatherPrefetch_ScalarPlusUnpacked32BitScaledOffsetsFixed | 0x00004000, 3090 PRFD_i_p_bz_d_x32_scaled = SVE64BitGatherPrefetch_ScalarPlusUnpacked32BitScaledOffsetsFixed | 0x00006000 3091 }; 3092 3093 enum SVE64BitGatherPrefetch_VectorPlusImmOp { 3094 SVE64BitGatherPrefetch_VectorPlusImmFixed = 0xC400E000, 3095 SVE64BitGatherPrefetch_VectorPlusImmFMask = 0xFE60E010, 3096 SVE64BitGatherPrefetch_VectorPlusImmMask = 0xFFE0E010, 3097 PRFB_i_p_ai_d = SVE64BitGatherPrefetch_VectorPlusImmFixed, 3098 PRFH_i_p_ai_d = SVE64BitGatherPrefetch_VectorPlusImmFixed | 0x00800000, 3099 PRFW_i_p_ai_d = SVE64BitGatherPrefetch_VectorPlusImmFixed | 0x01000000, 3100 PRFD_i_p_ai_d = SVE64BitGatherPrefetch_VectorPlusImmFixed | 0x01800000 3101 }; 3102 3103 enum SVE64BitScatterStore_ScalarPlus64BitScaledOffsetsOp { 3104 SVE64BitScatterStore_ScalarPlus64BitScaledOffsetsFixed = 0xE420A000, 3105 SVE64BitScatterStore_ScalarPlus64BitScaledOffsetsFMask = 0xFE60E000, 3106 SVE64BitScatterStore_ScalarPlus64BitScaledOffsetsMask = 0xFFE0E000, 3107 ST1H_z_p_bz_d_64_scaled = SVE64BitScatterStore_ScalarPlus64BitScaledOffsetsFixed | 0x00800000, 3108 ST1W_z_p_bz_d_64_scaled = SVE64BitScatterStore_ScalarPlus64BitScaledOffsetsFixed | 0x01000000, 3109 ST1D_z_p_bz_d_64_scaled = SVE64BitScatterStore_ScalarPlus64BitScaledOffsetsFixed | 0x01800000 3110 }; 3111 3112 enum SVE64BitScatterStore_ScalarPlus64BitUnscaledOffsetsOp { 3113 SVE64BitScatterStore_ScalarPlus64BitUnscaledOffsetsFixed = 0xE400A000, 3114 SVE64BitScatterStore_ScalarPlus64BitUnscaledOffsetsFMask = 0xFE60E000, 3115 SVE64BitScatterStore_ScalarPlus64BitUnscaledOffsetsMask = 0xFFE0E000, 3116 ST1B_z_p_bz_d_64_unscaled = SVE64BitScatterStore_ScalarPlus64BitUnscaledOffsetsFixed, 3117 ST1H_z_p_bz_d_64_unscaled = SVE64BitScatterStore_ScalarPlus64BitUnscaledOffsetsFixed | 0x00800000, 3118 ST1W_z_p_bz_d_64_unscaled = SVE64BitScatterStore_ScalarPlus64BitUnscaledOffsetsFixed | 0x01000000, 3119 ST1D_z_p_bz_d_64_unscaled = SVE64BitScatterStore_ScalarPlus64BitUnscaledOffsetsFixed | 0x01800000 3120 }; 3121 3122 enum SVE64BitScatterStore_ScalarPlusUnpacked32BitScaledOffsetsOp { 3123 SVE64BitScatterStore_ScalarPlusUnpacked32BitScaledOffsetsFixed = 0xE4208000, 3124 SVE64BitScatterStore_ScalarPlusUnpacked32BitScaledOffsetsFMask = 0xFE60A000, 3125 SVE64BitScatterStore_ScalarPlusUnpacked32BitScaledOffsetsMask = 0xFFE0A000, 3126 ST1H_z_p_bz_d_x32_scaled = SVE64BitScatterStore_ScalarPlusUnpacked32BitScaledOffsetsFixed | 0x00800000, 3127 ST1W_z_p_bz_d_x32_scaled = SVE64BitScatterStore_ScalarPlusUnpacked32BitScaledOffsetsFixed | 0x01000000, 3128 ST1D_z_p_bz_d_x32_scaled = SVE64BitScatterStore_ScalarPlusUnpacked32BitScaledOffsetsFixed | 0x01800000 3129 }; 3130 3131 enum SVE64BitScatterStore_ScalarPlusUnpacked32BitUnscaledOffsetsOp { 3132 SVE64BitScatterStore_ScalarPlusUnpacked32BitUnscaledOffsetsFixed = 0xE4008000, 3133 SVE64BitScatterStore_ScalarPlusUnpacked32BitUnscaledOffsetsFMask = 0xFE60A000, 3134 SVE64BitScatterStore_ScalarPlusUnpacked32BitUnscaledOffsetsMask = 0xFFE0A000, 3135 ST1B_z_p_bz_d_x32_unscaled = SVE64BitScatterStore_ScalarPlusUnpacked32BitUnscaledOffsetsFixed, 3136 ST1H_z_p_bz_d_x32_unscaled = SVE64BitScatterStore_ScalarPlusUnpacked32BitUnscaledOffsetsFixed | 0x00800000, 3137 ST1W_z_p_bz_d_x32_unscaled = SVE64BitScatterStore_ScalarPlusUnpacked32BitUnscaledOffsetsFixed | 0x01000000, 3138 ST1D_z_p_bz_d_x32_unscaled = SVE64BitScatterStore_ScalarPlusUnpacked32BitUnscaledOffsetsFixed | 0x01800000 3139 }; 3140 3141 enum SVE64BitScatterStore_VectorPlusImmOp { 3142 SVE64BitScatterStore_VectorPlusImmFixed = 0xE440A000, 3143 SVE64BitScatterStore_VectorPlusImmFMask = 0xFE60E000, 3144 SVE64BitScatterStore_VectorPlusImmMask = 0xFFE0E000, 3145 ST1B_z_p_ai_d = SVE64BitScatterStore_VectorPlusImmFixed, 3146 ST1H_z_p_ai_d = SVE64BitScatterStore_VectorPlusImmFixed | 0x00800000, 3147 ST1W_z_p_ai_d = SVE64BitScatterStore_VectorPlusImmFixed | 0x01000000, 3148 ST1D_z_p_ai_d = SVE64BitScatterStore_VectorPlusImmFixed | 0x01800000 3149 }; 3150 3151 enum SVEAddressGenerationOp { 3152 SVEAddressGenerationFixed = 0x0420A000, 3153 SVEAddressGenerationFMask = 0xFF20F000, 3154 SVEAddressGenerationMask = 0xFFE0F000, 3155 ADR_z_az_d_s32_scaled = SVEAddressGenerationFixed, 3156 ADR_z_az_d_u32_scaled = SVEAddressGenerationFixed | 0x00400000, 3157 ADR_z_az_s_same_scaled = SVEAddressGenerationFixed | 0x00800000, 3158 ADR_z_az_d_same_scaled = SVEAddressGenerationFixed | 0x00C00000 3159 }; 3160 3161 enum SVEBitwiseLogicalUnpredicatedOp { 3162 SVEBitwiseLogicalUnpredicatedFixed = 0x04202000, 3163 SVEBitwiseLogicalUnpredicatedFMask = 0xFF20E000, 3164 SVEBitwiseLogicalUnpredicatedMask = 0xFFE0FC00, 3165 AND_z_zz = SVEBitwiseLogicalUnpredicatedFixed | 0x00001000, 3166 ORR_z_zz = SVEBitwiseLogicalUnpredicatedFixed | 0x00401000, 3167 EOR_z_zz = SVEBitwiseLogicalUnpredicatedFixed | 0x00801000, 3168 BIC_z_zz = SVEBitwiseLogicalUnpredicatedFixed | 0x00C01000 3169 }; 3170 3171 enum SVEBitwiseLogicalWithImm_UnpredicatedOp { 3172 SVEBitwiseLogicalWithImm_UnpredicatedFixed = 0x05000000, 3173 SVEBitwiseLogicalWithImm_UnpredicatedFMask = 0xFF3C0000, 3174 SVEBitwiseLogicalWithImm_UnpredicatedMask = 0xFFFC0000, 3175 ORR_z_zi = SVEBitwiseLogicalWithImm_UnpredicatedFixed, 3176 EOR_z_zi = SVEBitwiseLogicalWithImm_UnpredicatedFixed | 0x00400000, 3177 AND_z_zi = SVEBitwiseLogicalWithImm_UnpredicatedFixed | 0x00800000 3178 }; 3179 3180 enum SVEBitwiseLogical_PredicatedOp { 3181 SVEBitwiseLogical_PredicatedFixed = 0x04180000, 3182 SVEBitwiseLogical_PredicatedFMask = 0xFF38E000, 3183 SVEBitwiseLogical_PredicatedMask = 0xFF3FE000, 3184 ORR_z_p_zz = SVEBitwiseLogical_PredicatedFixed, 3185 EOR_z_p_zz = SVEBitwiseLogical_PredicatedFixed | 0x00010000, 3186 AND_z_p_zz = SVEBitwiseLogical_PredicatedFixed | 0x00020000, 3187 BIC_z_p_zz = SVEBitwiseLogical_PredicatedFixed | 0x00030000 3188 }; 3189 3190 enum SVEBitwiseShiftByImm_PredicatedOp { 3191 SVEBitwiseShiftByImm_PredicatedFixed = 0x04008000, 3192 SVEBitwiseShiftByImm_PredicatedFMask = 0xFF30E000, 3193 SVEBitwiseShiftByImm_PredicatedMask = 0xFF3FE000, 3194 ASR_z_p_zi = SVEBitwiseShiftByImm_PredicatedFixed, 3195 LSR_z_p_zi = SVEBitwiseShiftByImm_PredicatedFixed | 0x00010000, 3196 LSL_z_p_zi = SVEBitwiseShiftByImm_PredicatedFixed | 0x00030000, 3197 ASRD_z_p_zi = SVEBitwiseShiftByImm_PredicatedFixed | 0x00040000 3198 }; 3199 3200 enum SVEBitwiseShiftByVector_PredicatedOp { 3201 SVEBitwiseShiftByVector_PredicatedFixed = 0x04108000, 3202 SVEBitwiseShiftByVector_PredicatedFMask = 0xFF38E000, 3203 SVEBitwiseShiftByVector_PredicatedMask = 0xFF3FE000, 3204 ASR_z_p_zz = SVEBitwiseShiftByVector_PredicatedFixed, 3205 LSR_z_p_zz = SVEBitwiseShiftByVector_PredicatedFixed | 0x00010000, 3206 LSL_z_p_zz = SVEBitwiseShiftByVector_PredicatedFixed | 0x00030000, 3207 ASRR_z_p_zz = SVEBitwiseShiftByVector_PredicatedFixed | 0x00040000, 3208 LSRR_z_p_zz = SVEBitwiseShiftByVector_PredicatedFixed | 0x00050000, 3209 LSLR_z_p_zz = SVEBitwiseShiftByVector_PredicatedFixed | 0x00070000 3210 }; 3211 3212 enum SVEBitwiseShiftByWideElements_PredicatedOp { 3213 SVEBitwiseShiftByWideElements_PredicatedFixed = 0x04188000, 3214 SVEBitwiseShiftByWideElements_PredicatedFMask = 0xFF38E000, 3215 SVEBitwiseShiftByWideElements_PredicatedMask = 0xFF3FE000, 3216 ASR_z_p_zw = SVEBitwiseShiftByWideElements_PredicatedFixed, 3217 LSR_z_p_zw = SVEBitwiseShiftByWideElements_PredicatedFixed | 0x00010000, 3218 LSL_z_p_zw = SVEBitwiseShiftByWideElements_PredicatedFixed | 0x00030000 3219 }; 3220 3221 enum SVEBitwiseShiftUnpredicatedOp { 3222 SVEBitwiseShiftUnpredicatedFixed = 0x04208000, 3223 SVEBitwiseShiftUnpredicatedFMask = 0xFF20E000, 3224 SVEBitwiseShiftUnpredicatedMask = 0xFF20FC00, 3225 ASR_z_zw = SVEBitwiseShiftUnpredicatedFixed, 3226 LSR_z_zw = SVEBitwiseShiftUnpredicatedFixed | 0x00000400, 3227 LSL_z_zw = SVEBitwiseShiftUnpredicatedFixed | 0x00000C00, 3228 ASR_z_zi = SVEBitwiseShiftUnpredicatedFixed | 0x00001000, 3229 LSR_z_zi = SVEBitwiseShiftUnpredicatedFixed | 0x00001400, 3230 LSL_z_zi = SVEBitwiseShiftUnpredicatedFixed | 0x00001C00 3231 }; 3232 3233 enum SVEBroadcastBitmaskImmOp { 3234 SVEBroadcastBitmaskImmFixed = 0x05C00000, 3235 SVEBroadcastBitmaskImmFMask = 0xFFFC0000, 3236 SVEBroadcastBitmaskImmMask = 0xFFFC0000, 3237 DUPM_z_i = SVEBroadcastBitmaskImmFixed 3238 }; 3239 3240 enum SVEBroadcastFPImm_UnpredicatedOp { 3241 SVEBroadcastFPImm_UnpredicatedFixed = 0x2539C000, 3242 SVEBroadcastFPImm_UnpredicatedFMask = 0xFF39C000, 3243 SVEBroadcastFPImm_UnpredicatedMask = 0xFF3FE000, 3244 FDUP_z_i = SVEBroadcastFPImm_UnpredicatedFixed 3245 }; 3246 3247 enum SVEBroadcastGeneralRegisterOp { 3248 SVEBroadcastGeneralRegisterFixed = 0x05203800, 3249 SVEBroadcastGeneralRegisterFMask = 0xFF3FFC00, 3250 SVEBroadcastGeneralRegisterMask = 0xFF3FFC00, 3251 DUP_z_r = SVEBroadcastGeneralRegisterFixed 3252 }; 3253 3254 enum SVEBroadcastIndexElementOp { 3255 SVEBroadcastIndexElementFixed = 0x05202000, 3256 SVEBroadcastIndexElementFMask = 0xFF20FC00, 3257 SVEBroadcastIndexElementMask = 0xFF20FC00, 3258 DUP_z_zi = SVEBroadcastIndexElementFixed 3259 }; 3260 3261 enum SVEBroadcastIntImm_UnpredicatedOp { 3262 SVEBroadcastIntImm_UnpredicatedFixed = 0x2538C000, 3263 SVEBroadcastIntImm_UnpredicatedFMask = 0xFF39C000, 3264 SVEBroadcastIntImm_UnpredicatedMask = 0xFF3FC000, 3265 DUP_z_i = SVEBroadcastIntImm_UnpredicatedFixed 3266 }; 3267 3268 enum SVECompressActiveElementsOp { 3269 SVECompressActiveElementsFixed = 0x05A18000, 3270 SVECompressActiveElementsFMask = 0xFFBFE000, 3271 SVECompressActiveElementsMask = 0xFFBFE000, 3272 COMPACT_z_p_z = SVECompressActiveElementsFixed 3273 }; 3274 3275 enum SVEConditionallyBroadcastElementToVectorOp { 3276 SVEConditionallyBroadcastElementToVectorFixed = 0x05288000, 3277 SVEConditionallyBroadcastElementToVectorFMask = 0xFF3EE000, 3278 SVEConditionallyBroadcastElementToVectorMask = 0xFF3FE000, 3279 CLASTA_z_p_zz = SVEConditionallyBroadcastElementToVectorFixed, 3280 CLASTB_z_p_zz = SVEConditionallyBroadcastElementToVectorFixed | 0x00010000 3281 }; 3282 3283 enum SVEConditionallyExtractElementToGeneralRegisterOp { 3284 SVEConditionallyExtractElementToGeneralRegisterFixed = 0x0530A000, 3285 SVEConditionallyExtractElementToGeneralRegisterFMask = 0xFF3EE000, 3286 SVEConditionallyExtractElementToGeneralRegisterMask = 0xFF3FE000, 3287 CLASTA_r_p_z = SVEConditionallyExtractElementToGeneralRegisterFixed, 3288 CLASTB_r_p_z = SVEConditionallyExtractElementToGeneralRegisterFixed | 0x00010000 3289 }; 3290 3291 enum SVEConditionallyExtractElementToSIMDFPScalarOp { 3292 SVEConditionallyExtractElementToSIMDFPScalarFixed = 0x052A8000, 3293 SVEConditionallyExtractElementToSIMDFPScalarFMask = 0xFF3EE000, 3294 SVEConditionallyExtractElementToSIMDFPScalarMask = 0xFF3FE000, 3295 CLASTA_v_p_z = SVEConditionallyExtractElementToSIMDFPScalarFixed, 3296 CLASTB_v_p_z = SVEConditionallyExtractElementToSIMDFPScalarFixed | 0x00010000 3297 }; 3298 3299 enum SVEConditionallyTerminateScalarsOp { 3300 SVEConditionallyTerminateScalarsFixed = 0x25202000, 3301 SVEConditionallyTerminateScalarsFMask = 0xFF20FC0F, 3302 SVEConditionallyTerminateScalarsMask = 0xFFA0FC1F, 3303 CTERMEQ_rr = SVEConditionallyTerminateScalarsFixed | 0x00800000, 3304 CTERMNE_rr = SVEConditionallyTerminateScalarsFixed | 0x00800010 3305 }; 3306 3307 enum SVEConstructivePrefix_UnpredicatedOp { 3308 SVEConstructivePrefix_UnpredicatedFixed = 0x0420BC00, 3309 SVEConstructivePrefix_UnpredicatedFMask = 0xFF20FC00, 3310 SVEConstructivePrefix_UnpredicatedMask = 0xFFFFFC00, 3311 MOVPRFX_z_z = SVEConstructivePrefix_UnpredicatedFixed 3312 }; 3313 3314 enum SVEContiguousFirstFaultLoad_ScalarPlusScalarOp { 3315 SVEContiguousFirstFaultLoad_ScalarPlusScalarFixed = 0xA4006000, 3316 SVEContiguousFirstFaultLoad_ScalarPlusScalarFMask = 0xFE00E000, 3317 SVEContiguousFirstFaultLoad_ScalarPlusScalarMask = 0xFFE0E000, 3318 LDFF1B_z_p_br_u8 = SVEContiguousFirstFaultLoad_ScalarPlusScalarFixed, 3319 LDFF1B_z_p_br_u16 = SVEContiguousFirstFaultLoad_ScalarPlusScalarFixed | 0x00200000, 3320 LDFF1B_z_p_br_u32 = SVEContiguousFirstFaultLoad_ScalarPlusScalarFixed | 0x00400000, 3321 LDFF1B_z_p_br_u64 = SVEContiguousFirstFaultLoad_ScalarPlusScalarFixed | 0x00600000, 3322 LDFF1SW_z_p_br_s64 = SVEContiguousFirstFaultLoad_ScalarPlusScalarFixed | 0x00800000, 3323 LDFF1H_z_p_br_u16 = SVEContiguousFirstFaultLoad_ScalarPlusScalarFixed | 0x00A00000, 3324 LDFF1H_z_p_br_u32 = SVEContiguousFirstFaultLoad_ScalarPlusScalarFixed | 0x00C00000, 3325 LDFF1H_z_p_br_u64 = SVEContiguousFirstFaultLoad_ScalarPlusScalarFixed | 0x00E00000, 3326 LDFF1SH_z_p_br_s64 = SVEContiguousFirstFaultLoad_ScalarPlusScalarFixed | 0x01000000, 3327 LDFF1SH_z_p_br_s32 = SVEContiguousFirstFaultLoad_ScalarPlusScalarFixed | 0x01200000, 3328 LDFF1W_z_p_br_u32 = SVEContiguousFirstFaultLoad_ScalarPlusScalarFixed | 0x01400000, 3329 LDFF1W_z_p_br_u64 = SVEContiguousFirstFaultLoad_ScalarPlusScalarFixed | 0x01600000, 3330 LDFF1SB_z_p_br_s64 = SVEContiguousFirstFaultLoad_ScalarPlusScalarFixed | 0x01800000, 3331 LDFF1SB_z_p_br_s32 = SVEContiguousFirstFaultLoad_ScalarPlusScalarFixed | 0x01A00000, 3332 LDFF1SB_z_p_br_s16 = SVEContiguousFirstFaultLoad_ScalarPlusScalarFixed | 0x01C00000, 3333 LDFF1D_z_p_br_u64 = SVEContiguousFirstFaultLoad_ScalarPlusScalarFixed | 0x01E00000 3334 }; 3335 3336 enum SVEContiguousLoad_ScalarPlusImmOp { 3337 SVEContiguousLoad_ScalarPlusImmFixed = 0xA400A000, 3338 SVEContiguousLoad_ScalarPlusImmFMask = 0xFE10E000, 3339 SVEContiguousLoad_ScalarPlusImmMask = 0xFFF0E000, 3340 LD1B_z_p_bi_u8 = SVEContiguousLoad_ScalarPlusImmFixed, 3341 LD1B_z_p_bi_u16 = SVEContiguousLoad_ScalarPlusImmFixed | 0x00200000, 3342 LD1B_z_p_bi_u32 = SVEContiguousLoad_ScalarPlusImmFixed | 0x00400000, 3343 LD1B_z_p_bi_u64 = SVEContiguousLoad_ScalarPlusImmFixed | 0x00600000, 3344 LD1SW_z_p_bi_s64 = SVEContiguousLoad_ScalarPlusImmFixed | 0x00800000, 3345 LD1H_z_p_bi_u16 = SVEContiguousLoad_ScalarPlusImmFixed | 0x00A00000, 3346 LD1H_z_p_bi_u32 = SVEContiguousLoad_ScalarPlusImmFixed | 0x00C00000, 3347 LD1H_z_p_bi_u64 = SVEContiguousLoad_ScalarPlusImmFixed | 0x00E00000, 3348 LD1SH_z_p_bi_s64 = SVEContiguousLoad_ScalarPlusImmFixed | 0x01000000, 3349 LD1SH_z_p_bi_s32 = SVEContiguousLoad_ScalarPlusImmFixed | 0x01200000, 3350 LD1W_z_p_bi_u32 = SVEContiguousLoad_ScalarPlusImmFixed | 0x01400000, 3351 LD1W_z_p_bi_u64 = SVEContiguousLoad_ScalarPlusImmFixed | 0x01600000, 3352 LD1SB_z_p_bi_s64 = SVEContiguousLoad_ScalarPlusImmFixed | 0x01800000, 3353 LD1SB_z_p_bi_s32 = SVEContiguousLoad_ScalarPlusImmFixed | 0x01A00000, 3354 LD1SB_z_p_bi_s16 = SVEContiguousLoad_ScalarPlusImmFixed | 0x01C00000, 3355 LD1D_z_p_bi_u64 = SVEContiguousLoad_ScalarPlusImmFixed | 0x01E00000 3356 }; 3357 3358 enum SVEContiguousLoad_ScalarPlusScalarOp { 3359 SVEContiguousLoad_ScalarPlusScalarFixed = 0xA4004000, 3360 SVEContiguousLoad_ScalarPlusScalarFMask = 0xFE00E000, 3361 SVEContiguousLoad_ScalarPlusScalarMask = 0xFFE0E000, 3362 LD1B_z_p_br_u8 = SVEContiguousLoad_ScalarPlusScalarFixed, 3363 LD1B_z_p_br_u16 = SVEContiguousLoad_ScalarPlusScalarFixed | 0x00200000, 3364 LD1B_z_p_br_u32 = SVEContiguousLoad_ScalarPlusScalarFixed | 0x00400000, 3365 LD1B_z_p_br_u64 = SVEContiguousLoad_ScalarPlusScalarFixed | 0x00600000, 3366 LD1SW_z_p_br_s64 = SVEContiguousLoad_ScalarPlusScalarFixed | 0x00800000, 3367 LD1H_z_p_br_u16 = SVEContiguousLoad_ScalarPlusScalarFixed | 0x00A00000, 3368 LD1H_z_p_br_u32 = SVEContiguousLoad_ScalarPlusScalarFixed | 0x00C00000, 3369 LD1H_z_p_br_u64 = SVEContiguousLoad_ScalarPlusScalarFixed | 0x00E00000, 3370 LD1SH_z_p_br_s64 = SVEContiguousLoad_ScalarPlusScalarFixed | 0x01000000, 3371 LD1SH_z_p_br_s32 = SVEContiguousLoad_ScalarPlusScalarFixed | 0x01200000, 3372 LD1W_z_p_br_u32 = SVEContiguousLoad_ScalarPlusScalarFixed | 0x01400000, 3373 LD1W_z_p_br_u64 = SVEContiguousLoad_ScalarPlusScalarFixed | 0x01600000, 3374 LD1SB_z_p_br_s64 = SVEContiguousLoad_ScalarPlusScalarFixed | 0x01800000, 3375 LD1SB_z_p_br_s32 = SVEContiguousLoad_ScalarPlusScalarFixed | 0x01A00000, 3376 LD1SB_z_p_br_s16 = SVEContiguousLoad_ScalarPlusScalarFixed | 0x01C00000, 3377 LD1D_z_p_br_u64 = SVEContiguousLoad_ScalarPlusScalarFixed | 0x01E00000 3378 }; 3379 3380 enum SVEContiguousNonFaultLoad_ScalarPlusImmOp { 3381 SVEContiguousNonFaultLoad_ScalarPlusImmFixed = 0xA410A000, 3382 SVEContiguousNonFaultLoad_ScalarPlusImmFMask = 0xFE10E000, 3383 SVEContiguousNonFaultLoad_ScalarPlusImmMask = 0xFFF0E000, 3384 LDNF1B_z_p_bi_u8 = SVEContiguousNonFaultLoad_ScalarPlusImmFixed, 3385 LDNF1B_z_p_bi_u16 = SVEContiguousNonFaultLoad_ScalarPlusImmFixed | 0x00200000, 3386 LDNF1B_z_p_bi_u32 = SVEContiguousNonFaultLoad_ScalarPlusImmFixed | 0x00400000, 3387 LDNF1B_z_p_bi_u64 = SVEContiguousNonFaultLoad_ScalarPlusImmFixed | 0x00600000, 3388 LDNF1SW_z_p_bi_s64 = SVEContiguousNonFaultLoad_ScalarPlusImmFixed | 0x00800000, 3389 LDNF1H_z_p_bi_u16 = SVEContiguousNonFaultLoad_ScalarPlusImmFixed | 0x00A00000, 3390 LDNF1H_z_p_bi_u32 = SVEContiguousNonFaultLoad_ScalarPlusImmFixed | 0x00C00000, 3391 LDNF1H_z_p_bi_u64 = SVEContiguousNonFaultLoad_ScalarPlusImmFixed | 0x00E00000, 3392 LDNF1SH_z_p_bi_s64 = SVEContiguousNonFaultLoad_ScalarPlusImmFixed | 0x01000000, 3393 LDNF1SH_z_p_bi_s32 = SVEContiguousNonFaultLoad_ScalarPlusImmFixed | 0x01200000, 3394 LDNF1W_z_p_bi_u32 = SVEContiguousNonFaultLoad_ScalarPlusImmFixed | 0x01400000, 3395 LDNF1W_z_p_bi_u64 = SVEContiguousNonFaultLoad_ScalarPlusImmFixed | 0x01600000, 3396 LDNF1SB_z_p_bi_s64 = SVEContiguousNonFaultLoad_ScalarPlusImmFixed | 0x01800000, 3397 LDNF1SB_z_p_bi_s32 = SVEContiguousNonFaultLoad_ScalarPlusImmFixed | 0x01A00000, 3398 LDNF1SB_z_p_bi_s16 = SVEContiguousNonFaultLoad_ScalarPlusImmFixed | 0x01C00000, 3399 LDNF1D_z_p_bi_u64 = SVEContiguousNonFaultLoad_ScalarPlusImmFixed | 0x01E00000 3400 }; 3401 3402 enum SVEContiguousNonTemporalLoad_ScalarPlusImmOp { 3403 SVEContiguousNonTemporalLoad_ScalarPlusImmFixed = 0xA400E000, 3404 SVEContiguousNonTemporalLoad_ScalarPlusImmFMask = 0xFE70E000, 3405 SVEContiguousNonTemporalLoad_ScalarPlusImmMask = 0xFFF0E000, 3406 LDNT1B_z_p_bi_contiguous = SVEContiguousNonTemporalLoad_ScalarPlusImmFixed, 3407 LDNT1H_z_p_bi_contiguous = SVEContiguousNonTemporalLoad_ScalarPlusImmFixed | 0x00800000, 3408 LDNT1W_z_p_bi_contiguous = SVEContiguousNonTemporalLoad_ScalarPlusImmFixed | 0x01000000, 3409 LDNT1D_z_p_bi_contiguous = SVEContiguousNonTemporalLoad_ScalarPlusImmFixed | 0x01800000 3410 }; 3411 3412 enum SVEContiguousNonTemporalLoad_ScalarPlusScalarOp { 3413 SVEContiguousNonTemporalLoad_ScalarPlusScalarFixed = 0xA400C000, 3414 SVEContiguousNonTemporalLoad_ScalarPlusScalarFMask = 0xFE60E000, 3415 SVEContiguousNonTemporalLoad_ScalarPlusScalarMask = 0xFFE0E000, 3416 LDNT1B_z_p_br_contiguous = SVEContiguousNonTemporalLoad_ScalarPlusScalarFixed, 3417 LDNT1H_z_p_br_contiguous = SVEContiguousNonTemporalLoad_ScalarPlusScalarFixed | 0x00800000, 3418 LDNT1W_z_p_br_contiguous = SVEContiguousNonTemporalLoad_ScalarPlusScalarFixed | 0x01000000, 3419 LDNT1D_z_p_br_contiguous = SVEContiguousNonTemporalLoad_ScalarPlusScalarFixed | 0x01800000 3420 }; 3421 3422 enum SVEContiguousNonTemporalStore_ScalarPlusImmOp { 3423 SVEContiguousNonTemporalStore_ScalarPlusImmFixed = 0xE410E000, 3424 SVEContiguousNonTemporalStore_ScalarPlusImmFMask = 0xFE70E000, 3425 SVEContiguousNonTemporalStore_ScalarPlusImmMask = 0xFFF0E000, 3426 STNT1B_z_p_bi_contiguous = SVEContiguousNonTemporalStore_ScalarPlusImmFixed, 3427 STNT1H_z_p_bi_contiguous = SVEContiguousNonTemporalStore_ScalarPlusImmFixed | 0x00800000, 3428 STNT1W_z_p_bi_contiguous = SVEContiguousNonTemporalStore_ScalarPlusImmFixed | 0x01000000, 3429 STNT1D_z_p_bi_contiguous = SVEContiguousNonTemporalStore_ScalarPlusImmFixed | 0x01800000 3430 }; 3431 3432 enum SVEContiguousNonTemporalStore_ScalarPlusScalarOp { 3433 SVEContiguousNonTemporalStore_ScalarPlusScalarFixed = 0xE4006000, 3434 SVEContiguousNonTemporalStore_ScalarPlusScalarFMask = 0xFE60E000, 3435 SVEContiguousNonTemporalStore_ScalarPlusScalarMask = 0xFFE0E000, 3436 STNT1B_z_p_br_contiguous = SVEContiguousNonTemporalStore_ScalarPlusScalarFixed, 3437 STNT1H_z_p_br_contiguous = SVEContiguousNonTemporalStore_ScalarPlusScalarFixed | 0x00800000, 3438 STNT1W_z_p_br_contiguous = SVEContiguousNonTemporalStore_ScalarPlusScalarFixed | 0x01000000, 3439 STNT1D_z_p_br_contiguous = SVEContiguousNonTemporalStore_ScalarPlusScalarFixed | 0x01800000 3440 }; 3441 3442 enum SVEContiguousPrefetch_ScalarPlusImmOp { 3443 SVEContiguousPrefetch_ScalarPlusImmFixed = 0x85C00000, 3444 SVEContiguousPrefetch_ScalarPlusImmFMask = 0xFFC08010, 3445 SVEContiguousPrefetch_ScalarPlusImmMask = 0xFFC0E010, 3446 PRFB_i_p_bi_s = SVEContiguousPrefetch_ScalarPlusImmFixed, 3447 PRFH_i_p_bi_s = SVEContiguousPrefetch_ScalarPlusImmFixed | 0x00002000, 3448 PRFW_i_p_bi_s = SVEContiguousPrefetch_ScalarPlusImmFixed | 0x00004000, 3449 PRFD_i_p_bi_s = SVEContiguousPrefetch_ScalarPlusImmFixed | 0x00006000 3450 }; 3451 3452 enum SVEContiguousPrefetch_ScalarPlusScalarOp { 3453 SVEContiguousPrefetch_ScalarPlusScalarFixed = 0x8400C000, 3454 SVEContiguousPrefetch_ScalarPlusScalarFMask = 0xFE60E010, 3455 SVEContiguousPrefetch_ScalarPlusScalarMask = 0xFFE0E010, 3456 PRFB_i_p_br_s = SVEContiguousPrefetch_ScalarPlusScalarFixed, 3457 PRFH_i_p_br_s = SVEContiguousPrefetch_ScalarPlusScalarFixed | 0x00800000, 3458 PRFW_i_p_br_s = SVEContiguousPrefetch_ScalarPlusScalarFixed | 0x01000000, 3459 PRFD_i_p_br_s = SVEContiguousPrefetch_ScalarPlusScalarFixed | 0x01800000 3460 }; 3461 3462 enum SVEContiguousStore_ScalarPlusImmOp { 3463 SVEContiguousStore_ScalarPlusImmFixed = 0xE400E000, 3464 SVEContiguousStore_ScalarPlusImmFMask = 0xFE10E000, 3465 SVEContiguousStore_ScalarPlusImmMask = 0xFF90E000, 3466 ST1B_z_p_bi = SVEContiguousStore_ScalarPlusImmFixed, 3467 ST1H_z_p_bi = SVEContiguousStore_ScalarPlusImmFixed | 0x00800000, 3468 ST1W_z_p_bi = SVEContiguousStore_ScalarPlusImmFixed | 0x01000000, 3469 ST1D_z_p_bi = SVEContiguousStore_ScalarPlusImmFixed | 0x01800000 3470 }; 3471 3472 enum SVEContiguousStore_ScalarPlusScalarOp { 3473 SVEContiguousStore_ScalarPlusScalarFixed = 0xE4004000, 3474 SVEContiguousStore_ScalarPlusScalarFMask = 0xFE00E000, 3475 SVEContiguousStore_ScalarPlusScalarMask = 0xFF80E000, 3476 ST1B_z_p_br = SVEContiguousStore_ScalarPlusScalarFixed, 3477 ST1H_z_p_br = SVEContiguousStore_ScalarPlusScalarFixed | 0x00800000, 3478 ST1W_z_p_br = SVEContiguousStore_ScalarPlusScalarFixed | 0x01000000, 3479 ST1D_z_p_br = SVEContiguousStore_ScalarPlusScalarFixed | 0x01800000 3480 }; 3481 3482 enum SVECopyFPImm_PredicatedOp { 3483 SVECopyFPImm_PredicatedFixed = 0x0510C000, 3484 SVECopyFPImm_PredicatedFMask = 0xFF30E000, 3485 SVECopyFPImm_PredicatedMask = 0xFF30E000, 3486 FCPY_z_p_i = SVECopyFPImm_PredicatedFixed 3487 }; 3488 3489 enum SVECopyGeneralRegisterToVector_PredicatedOp { 3490 SVECopyGeneralRegisterToVector_PredicatedFixed = 0x0528A000, 3491 SVECopyGeneralRegisterToVector_PredicatedFMask = 0xFF3FE000, 3492 SVECopyGeneralRegisterToVector_PredicatedMask = 0xFF3FE000, 3493 CPY_z_p_r = SVECopyGeneralRegisterToVector_PredicatedFixed 3494 }; 3495 3496 enum SVECopyIntImm_PredicatedOp { 3497 SVECopyIntImm_PredicatedFixed = 0x05100000, 3498 SVECopyIntImm_PredicatedFMask = 0xFF308000, 3499 SVECopyIntImm_PredicatedMask = 0xFF308000, 3500 CPY_z_p_i = SVECopyIntImm_PredicatedFixed 3501 }; 3502 3503 enum SVECopySIMDFPScalarRegisterToVector_PredicatedOp { 3504 SVECopySIMDFPScalarRegisterToVector_PredicatedFixed = 0x05208000, 3505 SVECopySIMDFPScalarRegisterToVector_PredicatedFMask = 0xFF3FE000, 3506 SVECopySIMDFPScalarRegisterToVector_PredicatedMask = 0xFF3FE000, 3507 CPY_z_p_v = SVECopySIMDFPScalarRegisterToVector_PredicatedFixed 3508 }; 3509 3510 enum SVEElementCountOp { 3511 SVEElementCountFixed = 0x0420E000, 3512 SVEElementCountFMask = 0xFF30F800, 3513 SVEElementCountMask = 0xFFF0FC00, 3514 CNTB_r_s = SVEElementCountFixed, 3515 CNTH_r_s = SVEElementCountFixed | 0x00400000, 3516 CNTW_r_s = SVEElementCountFixed | 0x00800000, 3517 CNTD_r_s = SVEElementCountFixed | 0x00C00000 3518 }; 3519 3520 enum SVEExtractElementToGeneralRegisterOp { 3521 SVEExtractElementToGeneralRegisterFixed = 0x0520A000, 3522 SVEExtractElementToGeneralRegisterFMask = 0xFF3EE000, 3523 SVEExtractElementToGeneralRegisterMask = 0xFF3FE000, 3524 LASTA_r_p_z = SVEExtractElementToGeneralRegisterFixed, 3525 LASTB_r_p_z = SVEExtractElementToGeneralRegisterFixed | 0x00010000 3526 }; 3527 3528 enum SVEExtractElementToSIMDFPScalarRegisterOp { 3529 SVEExtractElementToSIMDFPScalarRegisterFixed = 0x05228000, 3530 SVEExtractElementToSIMDFPScalarRegisterFMask = 0xFF3EE000, 3531 SVEExtractElementToSIMDFPScalarRegisterMask = 0xFF3FE000, 3532 LASTA_v_p_z = SVEExtractElementToSIMDFPScalarRegisterFixed, 3533 LASTB_v_p_z = SVEExtractElementToSIMDFPScalarRegisterFixed | 0x00010000 3534 }; 3535 3536 enum SVEFFRInitialiseOp { 3537 SVEFFRInitialiseFixed = 0x252C9000, 3538 SVEFFRInitialiseFMask = 0xFF3FFFFF, 3539 SVEFFRInitialiseMask = 0xFFFFFFFF, 3540 SETFFR_f = SVEFFRInitialiseFixed 3541 }; 3542 3543 enum SVEFFRWriteFromPredicateOp { 3544 SVEFFRWriteFromPredicateFixed = 0x25289000, 3545 SVEFFRWriteFromPredicateFMask = 0xFF3FFE1F, 3546 SVEFFRWriteFromPredicateMask = 0xFFFFFE1F, 3547 WRFFR_f_p = SVEFFRWriteFromPredicateFixed 3548 }; 3549 3550 enum SVEFPAccumulatingReductionOp { 3551 SVEFPAccumulatingReductionFixed = 0x65182000, 3552 SVEFPAccumulatingReductionFMask = 0xFF38E000, 3553 SVEFPAccumulatingReductionMask = 0xFF3FE000, 3554 FADDA_v_p_z = SVEFPAccumulatingReductionFixed 3555 }; 3556 3557 enum SVEFPArithmeticUnpredicatedOp { 3558 SVEFPArithmeticUnpredicatedFixed = 0x65000000, 3559 SVEFPArithmeticUnpredicatedFMask = 0xFF20E000, 3560 SVEFPArithmeticUnpredicatedMask = 0xFF20FC00, 3561 FADD_z_zz = SVEFPArithmeticUnpredicatedFixed, 3562 FSUB_z_zz = SVEFPArithmeticUnpredicatedFixed | 0x00000400, 3563 FMUL_z_zz = SVEFPArithmeticUnpredicatedFixed | 0x00000800, 3564 FTSMUL_z_zz = SVEFPArithmeticUnpredicatedFixed | 0x00000C00, 3565 FRECPS_z_zz = SVEFPArithmeticUnpredicatedFixed | 0x00001800, 3566 FRSQRTS_z_zz = SVEFPArithmeticUnpredicatedFixed | 0x00001C00 3567 }; 3568 3569 enum SVEFPArithmeticWithImm_PredicatedOp { 3570 SVEFPArithmeticWithImm_PredicatedFixed = 0x65188000, 3571 SVEFPArithmeticWithImm_PredicatedFMask = 0xFF38E3C0, 3572 SVEFPArithmeticWithImm_PredicatedMask = 0xFF3FE3C0, 3573 FADD_z_p_zs = SVEFPArithmeticWithImm_PredicatedFixed, 3574 FSUB_z_p_zs = SVEFPArithmeticWithImm_PredicatedFixed | 0x00010000, 3575 FMUL_z_p_zs = SVEFPArithmeticWithImm_PredicatedFixed | 0x00020000, 3576 FSUBR_z_p_zs = SVEFPArithmeticWithImm_PredicatedFixed | 0x00030000, 3577 FMAXNM_z_p_zs = SVEFPArithmeticWithImm_PredicatedFixed | 0x00040000, 3578 FMINNM_z_p_zs = SVEFPArithmeticWithImm_PredicatedFixed | 0x00050000, 3579 FMAX_z_p_zs = SVEFPArithmeticWithImm_PredicatedFixed | 0x00060000, 3580 FMIN_z_p_zs = SVEFPArithmeticWithImm_PredicatedFixed | 0x00070000 3581 }; 3582 3583 enum SVEFPArithmetic_PredicatedOp { 3584 SVEFPArithmetic_PredicatedFixed = 0x65008000, 3585 SVEFPArithmetic_PredicatedFMask = 0xFF30E000, 3586 SVEFPArithmetic_PredicatedMask = 0xFF3FE000, 3587 FADD_z_p_zz = SVEFPArithmetic_PredicatedFixed, 3588 FSUB_z_p_zz = SVEFPArithmetic_PredicatedFixed | 0x00010000, 3589 FMUL_z_p_zz = SVEFPArithmetic_PredicatedFixed | 0x00020000, 3590 FSUBR_z_p_zz = SVEFPArithmetic_PredicatedFixed | 0x00030000, 3591 FMAXNM_z_p_zz = SVEFPArithmetic_PredicatedFixed | 0x00040000, 3592 FMINNM_z_p_zz = SVEFPArithmetic_PredicatedFixed | 0x00050000, 3593 FMAX_z_p_zz = SVEFPArithmetic_PredicatedFixed | 0x00060000, 3594 FMIN_z_p_zz = SVEFPArithmetic_PredicatedFixed | 0x00070000, 3595 FABD_z_p_zz = SVEFPArithmetic_PredicatedFixed | 0x00080000, 3596 FSCALE_z_p_zz = SVEFPArithmetic_PredicatedFixed | 0x00090000, 3597 FMULX_z_p_zz = SVEFPArithmetic_PredicatedFixed | 0x000A0000, 3598 FDIVR_z_p_zz = SVEFPArithmetic_PredicatedFixed | 0x000C0000, 3599 FDIV_z_p_zz = SVEFPArithmetic_PredicatedFixed | 0x000D0000 3600 }; 3601 3602 enum SVEFPCompareVectorsOp { 3603 SVEFPCompareVectorsFixed = 0x65004000, 3604 SVEFPCompareVectorsFMask = 0xFF204000, 3605 SVEFPCompareVectorsMask = 0xFF20E010, 3606 FCMGE_p_p_zz = SVEFPCompareVectorsFixed, 3607 FCMGT_p_p_zz = SVEFPCompareVectorsFixed | 0x00000010, 3608 FCMEQ_p_p_zz = SVEFPCompareVectorsFixed | 0x00002000, 3609 FCMNE_p_p_zz = SVEFPCompareVectorsFixed | 0x00002010, 3610 FCMUO_p_p_zz = SVEFPCompareVectorsFixed | 0x00008000, 3611 FACGE_p_p_zz = SVEFPCompareVectorsFixed | 0x00008010, 3612 FACGT_p_p_zz = SVEFPCompareVectorsFixed | 0x0000A010 3613 }; 3614 3615 enum SVEFPCompareWithZeroOp { 3616 SVEFPCompareWithZeroFixed = 0x65102000, 3617 SVEFPCompareWithZeroFMask = 0xFF38E000, 3618 SVEFPCompareWithZeroMask = 0xFF3FE010, 3619 FCMGE_p_p_z0 = SVEFPCompareWithZeroFixed, 3620 FCMGT_p_p_z0 = SVEFPCompareWithZeroFixed | 0x00000010, 3621 FCMLT_p_p_z0 = SVEFPCompareWithZeroFixed | 0x00010000, 3622 FCMLE_p_p_z0 = SVEFPCompareWithZeroFixed | 0x00010010, 3623 FCMEQ_p_p_z0 = SVEFPCompareWithZeroFixed | 0x00020000, 3624 FCMNE_p_p_z0 = SVEFPCompareWithZeroFixed | 0x00030000 3625 }; 3626 3627 enum SVEFPComplexAdditionOp { 3628 SVEFPComplexAdditionFixed = 0x64008000, 3629 SVEFPComplexAdditionFMask = 0xFF3EE000, 3630 SVEFPComplexAdditionMask = 0xFF3EE000, 3631 FCADD_z_p_zz = SVEFPComplexAdditionFixed 3632 }; 3633 3634 enum SVEFPComplexMulAddOp { 3635 SVEFPComplexMulAddFixed = 0x64000000, 3636 SVEFPComplexMulAddFMask = 0xFF208000, 3637 SVEFPComplexMulAddMask = 0xFF208000, 3638 FCMLA_z_p_zzz = SVEFPComplexMulAddFixed 3639 }; 3640 3641 enum SVEFPComplexMulAddIndexOp { 3642 SVEFPComplexMulAddIndexFixed = 0x64201000, 3643 SVEFPComplexMulAddIndexFMask = 0xFF20F000, 3644 SVEFPComplexMulAddIndexMask = 0xFFE0F000, 3645 FCMLA_z_zzzi_h = SVEFPComplexMulAddIndexFixed | 0x00800000, 3646 FCMLA_z_zzzi_s = SVEFPComplexMulAddIndexFixed | 0x00C00000 3647 }; 3648 3649 enum SVEFPConvertPrecisionOp { 3650 SVEFPConvertPrecisionFixed = 0x6508A000, 3651 SVEFPConvertPrecisionFMask = 0xFF3CE000, 3652 SVEFPConvertPrecisionMask = 0xFFFFE000, 3653 FCVT_z_p_z_s2h = SVEFPConvertPrecisionFixed | 0x00800000, 3654 FCVT_z_p_z_h2s = SVEFPConvertPrecisionFixed | 0x00810000, 3655 FCVT_z_p_z_d2h = SVEFPConvertPrecisionFixed | 0x00C00000, 3656 FCVT_z_p_z_h2d = SVEFPConvertPrecisionFixed | 0x00C10000, 3657 FCVT_z_p_z_d2s = SVEFPConvertPrecisionFixed | 0x00C20000, 3658 FCVT_z_p_z_s2d = SVEFPConvertPrecisionFixed | 0x00C30000 3659 }; 3660 3661 enum SVEFPConvertToIntOp { 3662 SVEFPConvertToIntFixed = 0x6518A000, 3663 SVEFPConvertToIntFMask = 0xFF38E000, 3664 SVEFPConvertToIntMask = 0xFFFFE000, 3665 FCVTZS_z_p_z_fp162h = SVEFPConvertToIntFixed | 0x00420000, 3666 FCVTZU_z_p_z_fp162h = SVEFPConvertToIntFixed | 0x00430000, 3667 FCVTZS_z_p_z_fp162w = SVEFPConvertToIntFixed | 0x00440000, 3668 FCVTZU_z_p_z_fp162w = SVEFPConvertToIntFixed | 0x00450000, 3669 FCVTZS_z_p_z_fp162x = SVEFPConvertToIntFixed | 0x00460000, 3670 FCVTZU_z_p_z_fp162x = SVEFPConvertToIntFixed | 0x00470000, 3671 FCVTZS_z_p_z_s2w = SVEFPConvertToIntFixed | 0x00840000, 3672 FCVTZU_z_p_z_s2w = SVEFPConvertToIntFixed | 0x00850000, 3673 FCVTZS_z_p_z_d2w = SVEFPConvertToIntFixed | 0x00C00000, 3674 FCVTZU_z_p_z_d2w = SVEFPConvertToIntFixed | 0x00C10000, 3675 FCVTZS_z_p_z_s2x = SVEFPConvertToIntFixed | 0x00C40000, 3676 FCVTZU_z_p_z_s2x = SVEFPConvertToIntFixed | 0x00C50000, 3677 FCVTZS_z_p_z_d2x = SVEFPConvertToIntFixed | 0x00C60000, 3678 FCVTZU_z_p_z_d2x = SVEFPConvertToIntFixed | 0x00C70000 3679 }; 3680 3681 enum SVEFPExponentialAcceleratorOp { 3682 SVEFPExponentialAcceleratorFixed = 0x0420B800, 3683 SVEFPExponentialAcceleratorFMask = 0xFF20FC00, 3684 SVEFPExponentialAcceleratorMask = 0xFF3FFC00, 3685 FEXPA_z_z = SVEFPExponentialAcceleratorFixed 3686 }; 3687 3688 enum SVEFPFastReductionOp { 3689 SVEFPFastReductionFixed = 0x65002000, 3690 SVEFPFastReductionFMask = 0xFF38E000, 3691 SVEFPFastReductionMask = 0xFF3FE000, 3692 FADDV_v_p_z = SVEFPFastReductionFixed, 3693 FMAXNMV_v_p_z = SVEFPFastReductionFixed | 0x00040000, 3694 FMINNMV_v_p_z = SVEFPFastReductionFixed | 0x00050000, 3695 FMAXV_v_p_z = SVEFPFastReductionFixed | 0x00060000, 3696 FMINV_v_p_z = SVEFPFastReductionFixed | 0x00070000 3697 }; 3698 3699 enum SVEFPMulAddOp { 3700 SVEFPMulAddFixed = 0x65200000, 3701 SVEFPMulAddFMask = 0xFF200000, 3702 SVEFPMulAddMask = 0xFF20E000, 3703 FMLA_z_p_zzz = SVEFPMulAddFixed, 3704 FMLS_z_p_zzz = SVEFPMulAddFixed | 0x00002000, 3705 FNMLA_z_p_zzz = SVEFPMulAddFixed | 0x00004000, 3706 FNMLS_z_p_zzz = SVEFPMulAddFixed | 0x00006000, 3707 FMAD_z_p_zzz = SVEFPMulAddFixed | 0x00008000, 3708 FMSB_z_p_zzz = SVEFPMulAddFixed | 0x0000A000, 3709 FNMAD_z_p_zzz = SVEFPMulAddFixed | 0x0000C000, 3710 FNMSB_z_p_zzz = SVEFPMulAddFixed | 0x0000E000 3711 }; 3712 3713 enum SVEFPMulAddIndexOp { 3714 SVEFPMulAddIndexFixed = 0x64200000, 3715 SVEFPMulAddIndexFMask = 0xFF20F800, 3716 SVEFPMulAddIndexMask = 0xFFE0FC00, 3717 FMLA_z_zzzi_h = SVEFPMulAddIndexFixed, 3718 FMLA_z_zzzi_h_i3h = FMLA_z_zzzi_h | 0x00400000, 3719 FMLS_z_zzzi_h = SVEFPMulAddIndexFixed | 0x00000400, 3720 FMLS_z_zzzi_h_i3h = FMLS_z_zzzi_h | 0x00400000, 3721 FMLA_z_zzzi_s = SVEFPMulAddIndexFixed | 0x00800000, 3722 FMLS_z_zzzi_s = SVEFPMulAddIndexFixed | 0x00800400, 3723 FMLA_z_zzzi_d = SVEFPMulAddIndexFixed | 0x00C00000, 3724 FMLS_z_zzzi_d = SVEFPMulAddIndexFixed | 0x00C00400 3725 }; 3726 3727 enum SVEFPMulIndexOp { 3728 SVEFPMulIndexFixed = 0x64202000, 3729 SVEFPMulIndexFMask = 0xFF20FC00, 3730 SVEFPMulIndexMask = 0xFFE0FC00, 3731 FMUL_z_zzi_h = SVEFPMulIndexFixed, 3732 FMUL_z_zzi_h_i3h = FMUL_z_zzi_h | 0x00400000, 3733 FMUL_z_zzi_s = SVEFPMulIndexFixed | 0x00800000, 3734 FMUL_z_zzi_d = SVEFPMulIndexFixed | 0x00C00000 3735 }; 3736 3737 enum SVEFPRoundToIntegralValueOp { 3738 SVEFPRoundToIntegralValueFixed = 0x6500A000, 3739 SVEFPRoundToIntegralValueFMask = 0xFF38E000, 3740 SVEFPRoundToIntegralValueMask = 0xFF3FE000, 3741 FRINTN_z_p_z = SVEFPRoundToIntegralValueFixed, 3742 FRINTP_z_p_z = SVEFPRoundToIntegralValueFixed | 0x00010000, 3743 FRINTM_z_p_z = SVEFPRoundToIntegralValueFixed | 0x00020000, 3744 FRINTZ_z_p_z = SVEFPRoundToIntegralValueFixed | 0x00030000, 3745 FRINTA_z_p_z = SVEFPRoundToIntegralValueFixed | 0x00040000, 3746 FRINTX_z_p_z = SVEFPRoundToIntegralValueFixed | 0x00060000, 3747 FRINTI_z_p_z = SVEFPRoundToIntegralValueFixed | 0x00070000 3748 }; 3749 3750 enum SVEFPTrigMulAddCoefficientOp { 3751 SVEFPTrigMulAddCoefficientFixed = 0x65108000, 3752 SVEFPTrigMulAddCoefficientFMask = 0xFF38FC00, 3753 SVEFPTrigMulAddCoefficientMask = 0xFF38FC00, 3754 FTMAD_z_zzi = SVEFPTrigMulAddCoefficientFixed 3755 }; 3756 3757 enum SVEFPTrigSelectCoefficientOp { 3758 SVEFPTrigSelectCoefficientFixed = 0x0420B000, 3759 SVEFPTrigSelectCoefficientFMask = 0xFF20F800, 3760 SVEFPTrigSelectCoefficientMask = 0xFF20FC00, 3761 FTSSEL_z_zz = SVEFPTrigSelectCoefficientFixed 3762 }; 3763 3764 enum SVEFPUnaryOpOp { 3765 SVEFPUnaryOpFixed = 0x650CA000, 3766 SVEFPUnaryOpFMask = 0xFF3CE000, 3767 SVEFPUnaryOpMask = 0xFF3FE000, 3768 FRECPX_z_p_z = SVEFPUnaryOpFixed, 3769 FSQRT_z_p_z = SVEFPUnaryOpFixed | 0x00010000 3770 }; 3771 3772 enum SVEFPUnaryOpUnpredicatedOp { 3773 SVEFPUnaryOpUnpredicatedFixed = 0x65083000, 3774 SVEFPUnaryOpUnpredicatedFMask = 0xFF38F000, 3775 SVEFPUnaryOpUnpredicatedMask = 0xFF3FFC00, 3776 FRECPE_z_z = SVEFPUnaryOpUnpredicatedFixed | 0x00060000, 3777 FRSQRTE_z_z = SVEFPUnaryOpUnpredicatedFixed | 0x00070000 3778 }; 3779 3780 enum SVEIncDecByPredicateCountOp { 3781 SVEIncDecByPredicateCountFixed = 0x25288000, 3782 SVEIncDecByPredicateCountFMask = 0xFF38F000, 3783 SVEIncDecByPredicateCountMask = 0xFF3FFE00, 3784 SQINCP_z_p_z = SVEIncDecByPredicateCountFixed, 3785 SQINCP_r_p_r_sx = SVEIncDecByPredicateCountFixed | 0x00000800, 3786 SQINCP_r_p_r_x = SVEIncDecByPredicateCountFixed | 0x00000C00, 3787 UQINCP_z_p_z = SVEIncDecByPredicateCountFixed | 0x00010000, 3788 UQINCP_r_p_r_uw = SVEIncDecByPredicateCountFixed | 0x00010800, 3789 UQINCP_r_p_r_x = SVEIncDecByPredicateCountFixed | 0x00010C00, 3790 SQDECP_z_p_z = SVEIncDecByPredicateCountFixed | 0x00020000, 3791 SQDECP_r_p_r_sx = SVEIncDecByPredicateCountFixed | 0x00020800, 3792 SQDECP_r_p_r_x = SVEIncDecByPredicateCountFixed | 0x00020C00, 3793 UQDECP_z_p_z = SVEIncDecByPredicateCountFixed | 0x00030000, 3794 UQDECP_r_p_r_uw = SVEIncDecByPredicateCountFixed | 0x00030800, 3795 UQDECP_r_p_r_x = SVEIncDecByPredicateCountFixed | 0x00030C00, 3796 INCP_z_p_z = SVEIncDecByPredicateCountFixed | 0x00040000, 3797 INCP_r_p_r = SVEIncDecByPredicateCountFixed | 0x00040800, 3798 DECP_z_p_z = SVEIncDecByPredicateCountFixed | 0x00050000, 3799 DECP_r_p_r = SVEIncDecByPredicateCountFixed | 0x00050800 3800 }; 3801 3802 enum SVEIncDecRegisterByElementCountOp { 3803 SVEIncDecRegisterByElementCountFixed = 0x0430E000, 3804 SVEIncDecRegisterByElementCountFMask = 0xFF30F800, 3805 SVEIncDecRegisterByElementCountMask = 0xFFF0FC00, 3806 INCB_r_rs = SVEIncDecRegisterByElementCountFixed, 3807 DECB_r_rs = SVEIncDecRegisterByElementCountFixed | 0x00000400, 3808 INCH_r_rs = SVEIncDecRegisterByElementCountFixed | 0x00400000, 3809 DECH_r_rs = SVEIncDecRegisterByElementCountFixed | 0x00400400, 3810 INCW_r_rs = SVEIncDecRegisterByElementCountFixed | 0x00800000, 3811 DECW_r_rs = SVEIncDecRegisterByElementCountFixed | 0x00800400, 3812 INCD_r_rs = SVEIncDecRegisterByElementCountFixed | 0x00C00000, 3813 DECD_r_rs = SVEIncDecRegisterByElementCountFixed | 0x00C00400 3814 }; 3815 3816 enum SVEIncDecVectorByElementCountOp { 3817 SVEIncDecVectorByElementCountFixed = 0x0430C000, 3818 SVEIncDecVectorByElementCountFMask = 0xFF30F800, 3819 SVEIncDecVectorByElementCountMask = 0xFFF0FC00, 3820 INCH_z_zs = SVEIncDecVectorByElementCountFixed | 0x00400000, 3821 DECH_z_zs = SVEIncDecVectorByElementCountFixed | 0x00400400, 3822 INCW_z_zs = SVEIncDecVectorByElementCountFixed | 0x00800000, 3823 DECW_z_zs = SVEIncDecVectorByElementCountFixed | 0x00800400, 3824 INCD_z_zs = SVEIncDecVectorByElementCountFixed | 0x00C00000, 3825 DECD_z_zs = SVEIncDecVectorByElementCountFixed | 0x00C00400 3826 }; 3827 3828 enum SVEIndexGenerationOp { 3829 SVEIndexGenerationFixed = 0x04204000, 3830 SVEIndexGenerationFMask = 0xFF20F000, 3831 SVEIndexGenerationMask = 0xFF20FC00, 3832 INDEX_z_ii = SVEIndexGenerationFixed, 3833 INDEX_z_ri = SVEIndexGenerationFixed | 0x00000400, 3834 INDEX_z_ir = SVEIndexGenerationFixed | 0x00000800, 3835 INDEX_z_rr = SVEIndexGenerationFixed | 0x00000C00 3836 }; 3837 3838 enum SVEInsertGeneralRegisterOp { 3839 SVEInsertGeneralRegisterFixed = 0x05243800, 3840 SVEInsertGeneralRegisterFMask = 0xFF3FFC00, 3841 SVEInsertGeneralRegisterMask = 0xFF3FFC00, 3842 INSR_z_r = SVEInsertGeneralRegisterFixed 3843 }; 3844 3845 enum SVEInsertSIMDFPScalarRegisterOp { 3846 SVEInsertSIMDFPScalarRegisterFixed = 0x05343800, 3847 SVEInsertSIMDFPScalarRegisterFMask = 0xFF3FFC00, 3848 SVEInsertSIMDFPScalarRegisterMask = 0xFF3FFC00, 3849 INSR_z_v = SVEInsertSIMDFPScalarRegisterFixed 3850 }; 3851 3852 enum SVEIntAddSubtractImm_UnpredicatedOp { 3853 SVEIntAddSubtractImm_UnpredicatedFixed = 0x2520C000, 3854 SVEIntAddSubtractImm_UnpredicatedFMask = 0xFF38C000, 3855 SVEIntAddSubtractImm_UnpredicatedMask = 0xFF3FC000, 3856 ADD_z_zi = SVEIntAddSubtractImm_UnpredicatedFixed, 3857 SUB_z_zi = SVEIntAddSubtractImm_UnpredicatedFixed | 0x00010000, 3858 SUBR_z_zi = SVEIntAddSubtractImm_UnpredicatedFixed | 0x00030000, 3859 SQADD_z_zi = SVEIntAddSubtractImm_UnpredicatedFixed | 0x00040000, 3860 UQADD_z_zi = SVEIntAddSubtractImm_UnpredicatedFixed | 0x00050000, 3861 SQSUB_z_zi = SVEIntAddSubtractImm_UnpredicatedFixed | 0x00060000, 3862 UQSUB_z_zi = SVEIntAddSubtractImm_UnpredicatedFixed | 0x00070000 3863 }; 3864 3865 enum SVEIntAddSubtractVectors_PredicatedOp { 3866 SVEIntAddSubtractVectors_PredicatedFixed = 0x04000000, 3867 SVEIntAddSubtractVectors_PredicatedFMask = 0xFF38E000, 3868 SVEIntAddSubtractVectors_PredicatedMask = 0xFF3FE000, 3869 ADD_z_p_zz = SVEIntAddSubtractVectors_PredicatedFixed, 3870 SUB_z_p_zz = SVEIntAddSubtractVectors_PredicatedFixed | 0x00010000, 3871 SUBR_z_p_zz = SVEIntAddSubtractVectors_PredicatedFixed | 0x00030000 3872 }; 3873 3874 enum SVEIntArithmeticUnpredicatedOp { 3875 SVEIntArithmeticUnpredicatedFixed = 0x04200000, 3876 SVEIntArithmeticUnpredicatedFMask = 0xFF20E000, 3877 SVEIntArithmeticUnpredicatedMask = 0xFF20FC00, 3878 ADD_z_zz = SVEIntArithmeticUnpredicatedFixed, 3879 SUB_z_zz = SVEIntArithmeticUnpredicatedFixed | 0x00000400, 3880 SQADD_z_zz = SVEIntArithmeticUnpredicatedFixed | 0x00001000, 3881 UQADD_z_zz = SVEIntArithmeticUnpredicatedFixed | 0x00001400, 3882 SQSUB_z_zz = SVEIntArithmeticUnpredicatedFixed | 0x00001800, 3883 UQSUB_z_zz = SVEIntArithmeticUnpredicatedFixed | 0x00001C00 3884 }; 3885 3886 enum SVEIntCompareScalarCountAndLimitOp { 3887 SVEIntCompareScalarCountAndLimitFixed = 0x25200000, 3888 SVEIntCompareScalarCountAndLimitFMask = 0xFF20E000, 3889 SVEIntCompareScalarCountAndLimitMask = 0xFF20EC10, 3890 WHILELT_p_p_rr = SVEIntCompareScalarCountAndLimitFixed | 0x00000400, 3891 WHILELE_p_p_rr = SVEIntCompareScalarCountAndLimitFixed | 0x00000410, 3892 WHILELO_p_p_rr = SVEIntCompareScalarCountAndLimitFixed | 0x00000C00, 3893 WHILELS_p_p_rr = SVEIntCompareScalarCountAndLimitFixed | 0x00000C10 3894 }; 3895 3896 enum SVEIntCompareSignedImmOp { 3897 SVEIntCompareSignedImmFixed = 0x25000000, 3898 SVEIntCompareSignedImmFMask = 0xFF204000, 3899 SVEIntCompareSignedImmMask = 0xFF20E010, 3900 CMPGE_p_p_zi = SVEIntCompareSignedImmFixed, 3901 CMPGT_p_p_zi = SVEIntCompareSignedImmFixed | 0x00000010, 3902 CMPLT_p_p_zi = SVEIntCompareSignedImmFixed | 0x00002000, 3903 CMPLE_p_p_zi = SVEIntCompareSignedImmFixed | 0x00002010, 3904 CMPEQ_p_p_zi = SVEIntCompareSignedImmFixed | 0x00008000, 3905 CMPNE_p_p_zi = SVEIntCompareSignedImmFixed | 0x00008010 3906 }; 3907 3908 enum SVEIntCompareUnsignedImmOp { 3909 SVEIntCompareUnsignedImmFixed = 0x24200000, 3910 SVEIntCompareUnsignedImmFMask = 0xFF200000, 3911 SVEIntCompareUnsignedImmMask = 0xFF202010, 3912 CMPHS_p_p_zi = SVEIntCompareUnsignedImmFixed, 3913 CMPHI_p_p_zi = SVEIntCompareUnsignedImmFixed | 0x00000010, 3914 CMPLO_p_p_zi = SVEIntCompareUnsignedImmFixed | 0x00002000, 3915 CMPLS_p_p_zi = SVEIntCompareUnsignedImmFixed | 0x00002010 3916 }; 3917 3918 enum SVEIntCompareVectorsOp { 3919 SVEIntCompareVectorsFixed = 0x24000000, 3920 SVEIntCompareVectorsFMask = 0xFF200000, 3921 SVEIntCompareVectorsMask = 0xFF20E010, 3922 CMPHS_p_p_zz = SVEIntCompareVectorsFixed, 3923 CMPHI_p_p_zz = SVEIntCompareVectorsFixed | 0x00000010, 3924 CMPEQ_p_p_zw = SVEIntCompareVectorsFixed | 0x00002000, 3925 CMPNE_p_p_zw = SVEIntCompareVectorsFixed | 0x00002010, 3926 CMPGE_p_p_zw = SVEIntCompareVectorsFixed | 0x00004000, 3927 CMPGT_p_p_zw = SVEIntCompareVectorsFixed | 0x00004010, 3928 CMPLT_p_p_zw = SVEIntCompareVectorsFixed | 0x00006000, 3929 CMPLE_p_p_zw = SVEIntCompareVectorsFixed | 0x00006010, 3930 CMPGE_p_p_zz = SVEIntCompareVectorsFixed | 0x00008000, 3931 CMPGT_p_p_zz = SVEIntCompareVectorsFixed | 0x00008010, 3932 CMPEQ_p_p_zz = SVEIntCompareVectorsFixed | 0x0000A000, 3933 CMPNE_p_p_zz = SVEIntCompareVectorsFixed | 0x0000A010, 3934 CMPHS_p_p_zw = SVEIntCompareVectorsFixed | 0x0000C000, 3935 CMPHI_p_p_zw = SVEIntCompareVectorsFixed | 0x0000C010, 3936 CMPLO_p_p_zw = SVEIntCompareVectorsFixed | 0x0000E000, 3937 CMPLS_p_p_zw = SVEIntCompareVectorsFixed | 0x0000E010 3938 }; 3939 3940 enum SVEIntConvertToFPOp { 3941 SVEIntConvertToFPFixed = 0x6510A000, 3942 SVEIntConvertToFPFMask = 0xFF38E000, 3943 SVEIntConvertToFPMask = 0xFFFFE000, 3944 SCVTF_z_p_z_h2fp16 = SVEIntConvertToFPFixed | 0x00420000, 3945 UCVTF_z_p_z_h2fp16 = SVEIntConvertToFPFixed | 0x00430000, 3946 SCVTF_z_p_z_w2fp16 = SVEIntConvertToFPFixed | 0x00440000, 3947 UCVTF_z_p_z_w2fp16 = SVEIntConvertToFPFixed | 0x00450000, 3948 SCVTF_z_p_z_x2fp16 = SVEIntConvertToFPFixed | 0x00460000, 3949 UCVTF_z_p_z_x2fp16 = SVEIntConvertToFPFixed | 0x00470000, 3950 SCVTF_z_p_z_w2s = SVEIntConvertToFPFixed | 0x00840000, 3951 UCVTF_z_p_z_w2s = SVEIntConvertToFPFixed | 0x00850000, 3952 SCVTF_z_p_z_w2d = SVEIntConvertToFPFixed | 0x00C00000, 3953 UCVTF_z_p_z_w2d = SVEIntConvertToFPFixed | 0x00C10000, 3954 SCVTF_z_p_z_x2s = SVEIntConvertToFPFixed | 0x00C40000, 3955 UCVTF_z_p_z_x2s = SVEIntConvertToFPFixed | 0x00C50000, 3956 SCVTF_z_p_z_x2d = SVEIntConvertToFPFixed | 0x00C60000, 3957 UCVTF_z_p_z_x2d = SVEIntConvertToFPFixed | 0x00C70000 3958 }; 3959 3960 enum SVEIntDivideVectors_PredicatedOp { 3961 SVEIntDivideVectors_PredicatedFixed = 0x04140000, 3962 SVEIntDivideVectors_PredicatedFMask = 0xFF3CE000, 3963 SVEIntDivideVectors_PredicatedMask = 0xFF3FE000, 3964 SDIV_z_p_zz = SVEIntDivideVectors_PredicatedFixed, 3965 UDIV_z_p_zz = SVEIntDivideVectors_PredicatedFixed | 0x00010000, 3966 SDIVR_z_p_zz = SVEIntDivideVectors_PredicatedFixed | 0x00020000, 3967 UDIVR_z_p_zz = SVEIntDivideVectors_PredicatedFixed | 0x00030000 3968 }; 3969 3970 enum SVEIntMinMaxDifference_PredicatedOp { 3971 SVEIntMinMaxDifference_PredicatedFixed = 0x04080000, 3972 SVEIntMinMaxDifference_PredicatedFMask = 0xFF38E000, 3973 SVEIntMinMaxDifference_PredicatedMask = 0xFF3FE000, 3974 SMAX_z_p_zz = SVEIntMinMaxDifference_PredicatedFixed, 3975 UMAX_z_p_zz = SVEIntMinMaxDifference_PredicatedFixed | 0x00010000, 3976 SMIN_z_p_zz = SVEIntMinMaxDifference_PredicatedFixed | 0x00020000, 3977 UMIN_z_p_zz = SVEIntMinMaxDifference_PredicatedFixed | 0x00030000, 3978 SABD_z_p_zz = SVEIntMinMaxDifference_PredicatedFixed | 0x00040000, 3979 UABD_z_p_zz = SVEIntMinMaxDifference_PredicatedFixed | 0x00050000 3980 }; 3981 3982 enum SVEIntMinMaxImm_UnpredicatedOp { 3983 SVEIntMinMaxImm_UnpredicatedFixed = 0x2528C000, 3984 SVEIntMinMaxImm_UnpredicatedFMask = 0xFF38C000, 3985 SVEIntMinMaxImm_UnpredicatedMask = 0xFF3FE000, 3986 SMAX_z_zi = SVEIntMinMaxImm_UnpredicatedFixed, 3987 UMAX_z_zi = SVEIntMinMaxImm_UnpredicatedFixed | 0x00010000, 3988 SMIN_z_zi = SVEIntMinMaxImm_UnpredicatedFixed | 0x00020000, 3989 UMIN_z_zi = SVEIntMinMaxImm_UnpredicatedFixed | 0x00030000 3990 }; 3991 3992 enum SVEIntMulAddPredicatedOp { 3993 SVEIntMulAddPredicatedFixed = 0x04004000, 3994 SVEIntMulAddPredicatedFMask = 0xFF204000, 3995 SVEIntMulAddPredicatedMask = 0xFF20E000, 3996 MLA_z_p_zzz = SVEIntMulAddPredicatedFixed, 3997 MLS_z_p_zzz = SVEIntMulAddPredicatedFixed | 0x00002000, 3998 MAD_z_p_zzz = SVEIntMulAddPredicatedFixed | 0x00008000, 3999 MSB_z_p_zzz = SVEIntMulAddPredicatedFixed | 0x0000A000 4000 }; 4001 4002 enum SVEIntMulAddUnpredicatedOp { 4003 SVEIntMulAddUnpredicatedFixed = 0x44000000, 4004 SVEIntMulAddUnpredicatedFMask = 0xFF208000, 4005 SVEIntMulAddUnpredicatedMask = 0xFF20FC00, 4006 SDOT_z_zzz = SVEIntMulAddUnpredicatedFixed, 4007 UDOT_z_zzz = SVEIntMulAddUnpredicatedFixed | 0x00000400 4008 }; 4009 4010 enum SVEIntMulImm_UnpredicatedOp { 4011 SVEIntMulImm_UnpredicatedFixed = 0x2530C000, 4012 SVEIntMulImm_UnpredicatedFMask = 0xFF38C000, 4013 SVEIntMulImm_UnpredicatedMask = 0xFF3FE000, 4014 MUL_z_zi = SVEIntMulImm_UnpredicatedFixed 4015 }; 4016 4017 enum SVEIntMulVectors_PredicatedOp { 4018 SVEIntMulVectors_PredicatedFixed = 0x04100000, 4019 SVEIntMulVectors_PredicatedFMask = 0xFF3CE000, 4020 SVEIntMulVectors_PredicatedMask = 0xFF3FE000, 4021 MUL_z_p_zz = SVEIntMulVectors_PredicatedFixed, 4022 SMULH_z_p_zz = SVEIntMulVectors_PredicatedFixed | 0x00020000, 4023 UMULH_z_p_zz = SVEIntMulVectors_PredicatedFixed | 0x00030000 4024 }; 4025 4026 enum SVEMovprfxOp { 4027 SVEMovprfxFixed = 0x04002000, 4028 SVEMovprfxFMask = 0xFF20E000, 4029 SVEMovprfxMask = 0xFF3EE000, 4030 MOVPRFX_z_p_z = SVEMovprfxFixed | 0x00100000 4031 }; 4032 4033 enum SVEIntReductionOp { 4034 SVEIntReductionFixed = 0x04002000, 4035 SVEIntReductionFMask = 0xFF20E000, 4036 SVEIntReductionMask = 0xFF3FE000, 4037 SADDV_r_p_z = SVEIntReductionFixed, 4038 UADDV_r_p_z = SVEIntReductionFixed | 0x00010000, 4039 SMAXV_r_p_z = SVEIntReductionFixed | 0x00080000, 4040 UMAXV_r_p_z = SVEIntReductionFixed | 0x00090000, 4041 SMINV_r_p_z = SVEIntReductionFixed | 0x000A0000, 4042 UMINV_r_p_z = SVEIntReductionFixed | 0x000B0000 4043 }; 4044 4045 enum SVEIntReductionLogicalOp { 4046 SVEIntReductionLogicalFixed = 0x04182000, 4047 SVEIntReductionLogicalFMask = 0xFF38E000, 4048 SVEIntReductionLogicalMask = 0xFF3FE000, 4049 ORV_r_p_z = SVEIntReductionLogicalFixed | 0x00180000, 4050 EORV_r_p_z = SVEIntReductionLogicalFixed | 0x00190000, 4051 ANDV_r_p_z = SVEIntReductionLogicalFixed | 0x001A0000 4052 }; 4053 4054 enum SVEIntUnaryArithmeticPredicatedOp { 4055 SVEIntUnaryArithmeticPredicatedFixed = 0x0400A000, 4056 SVEIntUnaryArithmeticPredicatedFMask = 0xFF20E000, 4057 SVEIntUnaryArithmeticPredicatedMask = 0xFF3FE000, 4058 SXTB_z_p_z = SVEIntUnaryArithmeticPredicatedFixed | 0x00100000, 4059 UXTB_z_p_z = SVEIntUnaryArithmeticPredicatedFixed | 0x00110000, 4060 SXTH_z_p_z = SVEIntUnaryArithmeticPredicatedFixed | 0x00120000, 4061 UXTH_z_p_z = SVEIntUnaryArithmeticPredicatedFixed | 0x00130000, 4062 SXTW_z_p_z = SVEIntUnaryArithmeticPredicatedFixed | 0x00140000, 4063 UXTW_z_p_z = SVEIntUnaryArithmeticPredicatedFixed | 0x00150000, 4064 ABS_z_p_z = SVEIntUnaryArithmeticPredicatedFixed | 0x00160000, 4065 NEG_z_p_z = SVEIntUnaryArithmeticPredicatedFixed | 0x00170000, 4066 CLS_z_p_z = SVEIntUnaryArithmeticPredicatedFixed | 0x00180000, 4067 CLZ_z_p_z = SVEIntUnaryArithmeticPredicatedFixed | 0x00190000, 4068 CNT_z_p_z = SVEIntUnaryArithmeticPredicatedFixed | 0x001A0000, 4069 CNOT_z_p_z = SVEIntUnaryArithmeticPredicatedFixed | 0x001B0000, 4070 FABS_z_p_z = SVEIntUnaryArithmeticPredicatedFixed | 0x001C0000, 4071 FNEG_z_p_z = SVEIntUnaryArithmeticPredicatedFixed | 0x001D0000, 4072 NOT_z_p_z = SVEIntUnaryArithmeticPredicatedFixed | 0x001E0000 4073 }; 4074 4075 enum SVELoadAndBroadcastElementOp { 4076 SVELoadAndBroadcastElementFixed = 0x84408000, 4077 SVELoadAndBroadcastElementFMask = 0xFE408000, 4078 SVELoadAndBroadcastElementMask = 0xFFC0E000, 4079 LD1RB_z_p_bi_u8 = SVELoadAndBroadcastElementFixed, 4080 LD1RB_z_p_bi_u16 = SVELoadAndBroadcastElementFixed | 0x00002000, 4081 LD1RB_z_p_bi_u32 = SVELoadAndBroadcastElementFixed | 0x00004000, 4082 LD1RB_z_p_bi_u64 = SVELoadAndBroadcastElementFixed | 0x00006000, 4083 LD1RSW_z_p_bi_s64 = SVELoadAndBroadcastElementFixed | 0x00800000, 4084 LD1RH_z_p_bi_u16 = SVELoadAndBroadcastElementFixed | 0x00802000, 4085 LD1RH_z_p_bi_u32 = SVELoadAndBroadcastElementFixed | 0x00804000, 4086 LD1RH_z_p_bi_u64 = SVELoadAndBroadcastElementFixed | 0x00806000, 4087 LD1RSH_z_p_bi_s64 = SVELoadAndBroadcastElementFixed | 0x01000000, 4088 LD1RSH_z_p_bi_s32 = SVELoadAndBroadcastElementFixed | 0x01002000, 4089 LD1RW_z_p_bi_u32 = SVELoadAndBroadcastElementFixed | 0x01004000, 4090 LD1RW_z_p_bi_u64 = SVELoadAndBroadcastElementFixed | 0x01006000, 4091 LD1RSB_z_p_bi_s64 = SVELoadAndBroadcastElementFixed | 0x01800000, 4092 LD1RSB_z_p_bi_s32 = SVELoadAndBroadcastElementFixed | 0x01802000, 4093 LD1RSB_z_p_bi_s16 = SVELoadAndBroadcastElementFixed | 0x01804000, 4094 LD1RD_z_p_bi_u64 = SVELoadAndBroadcastElementFixed | 0x01806000 4095 }; 4096 4097 enum SVELoadAndBroadcastQuadword_ScalarPlusImmOp { 4098 SVELoadAndBroadcastQuadword_ScalarPlusImmFixed = 0xA4002000, 4099 SVELoadAndBroadcastQuadword_ScalarPlusImmFMask = 0xFE10E000, 4100 SVELoadAndBroadcastQuadword_ScalarPlusImmMask = 0xFFF0E000, 4101 LD1RQB_z_p_bi_u8 = SVELoadAndBroadcastQuadword_ScalarPlusImmFixed, 4102 LD1RQH_z_p_bi_u16 = SVELoadAndBroadcastQuadword_ScalarPlusImmFixed | 0x00800000, 4103 LD1RQW_z_p_bi_u32 = SVELoadAndBroadcastQuadword_ScalarPlusImmFixed | 0x01000000, 4104 LD1RQD_z_p_bi_u64 = SVELoadAndBroadcastQuadword_ScalarPlusImmFixed | 0x01800000 4105 }; 4106 4107 enum SVELoadAndBroadcastQuadword_ScalarPlusScalarOp { 4108 SVELoadAndBroadcastQuadword_ScalarPlusScalarFixed = 0xA4000000, 4109 SVELoadAndBroadcastQuadword_ScalarPlusScalarFMask = 0xFE00E000, 4110 SVELoadAndBroadcastQuadword_ScalarPlusScalarMask = 0xFFE0E000, 4111 LD1RQB_z_p_br_contiguous = SVELoadAndBroadcastQuadword_ScalarPlusScalarFixed, 4112 LD1RQH_z_p_br_contiguous = SVELoadAndBroadcastQuadword_ScalarPlusScalarFixed | 0x00800000, 4113 LD1RQW_z_p_br_contiguous = SVELoadAndBroadcastQuadword_ScalarPlusScalarFixed | 0x01000000, 4114 LD1RQD_z_p_br_contiguous = SVELoadAndBroadcastQuadword_ScalarPlusScalarFixed | 0x01800000 4115 }; 4116 4117 enum SVELoadMultipleStructures_ScalarPlusImmOp { 4118 SVELoadMultipleStructures_ScalarPlusImmFixed = 0xA400E000, 4119 SVELoadMultipleStructures_ScalarPlusImmFMask = 0xFE10E000, 4120 SVELoadMultipleStructures_ScalarPlusImmMask = 0xFFF0E000, 4121 LD2B_z_p_bi_contiguous = SVELoadMultipleStructures_ScalarPlusImmFixed | 0x00200000, 4122 LD3B_z_p_bi_contiguous = SVELoadMultipleStructures_ScalarPlusImmFixed | 0x00400000, 4123 LD4B_z_p_bi_contiguous = SVELoadMultipleStructures_ScalarPlusImmFixed | 0x00600000, 4124 LD2H_z_p_bi_contiguous = SVELoadMultipleStructures_ScalarPlusImmFixed | 0x00A00000, 4125 LD3H_z_p_bi_contiguous = SVELoadMultipleStructures_ScalarPlusImmFixed | 0x00C00000, 4126 LD4H_z_p_bi_contiguous = SVELoadMultipleStructures_ScalarPlusImmFixed | 0x00E00000, 4127 LD2W_z_p_bi_contiguous = SVELoadMultipleStructures_ScalarPlusImmFixed | 0x01200000, 4128 LD3W_z_p_bi_contiguous = SVELoadMultipleStructures_ScalarPlusImmFixed | 0x01400000, 4129 LD4W_z_p_bi_contiguous = SVELoadMultipleStructures_ScalarPlusImmFixed | 0x01600000, 4130 LD2D_z_p_bi_contiguous = SVELoadMultipleStructures_ScalarPlusImmFixed | 0x01A00000, 4131 LD3D_z_p_bi_contiguous = SVELoadMultipleStructures_ScalarPlusImmFixed | 0x01C00000, 4132 LD4D_z_p_bi_contiguous = SVELoadMultipleStructures_ScalarPlusImmFixed | 0x01E00000 4133 }; 4134 4135 enum SVELoadMultipleStructures_ScalarPlusScalarOp { 4136 SVELoadMultipleStructures_ScalarPlusScalarFixed = 0xA400C000, 4137 SVELoadMultipleStructures_ScalarPlusScalarFMask = 0xFE00E000, 4138 SVELoadMultipleStructures_ScalarPlusScalarMask = 0xFFE0E000, 4139 LD2B_z_p_br_contiguous = SVELoadMultipleStructures_ScalarPlusScalarFixed | 0x00200000, 4140 LD3B_z_p_br_contiguous = SVELoadMultipleStructures_ScalarPlusScalarFixed | 0x00400000, 4141 LD4B_z_p_br_contiguous = SVELoadMultipleStructures_ScalarPlusScalarFixed | 0x00600000, 4142 LD2H_z_p_br_contiguous = SVELoadMultipleStructures_ScalarPlusScalarFixed | 0x00A00000, 4143 LD3H_z_p_br_contiguous = SVELoadMultipleStructures_ScalarPlusScalarFixed | 0x00C00000, 4144 LD4H_z_p_br_contiguous = SVELoadMultipleStructures_ScalarPlusScalarFixed | 0x00E00000, 4145 LD2W_z_p_br_contiguous = SVELoadMultipleStructures_ScalarPlusScalarFixed | 0x01200000, 4146 LD3W_z_p_br_contiguous = SVELoadMultipleStructures_ScalarPlusScalarFixed | 0x01400000, 4147 LD4W_z_p_br_contiguous = SVELoadMultipleStructures_ScalarPlusScalarFixed | 0x01600000, 4148 LD2D_z_p_br_contiguous = SVELoadMultipleStructures_ScalarPlusScalarFixed | 0x01A00000, 4149 LD3D_z_p_br_contiguous = SVELoadMultipleStructures_ScalarPlusScalarFixed | 0x01C00000, 4150 LD4D_z_p_br_contiguous = SVELoadMultipleStructures_ScalarPlusScalarFixed | 0x01E00000 4151 }; 4152 4153 enum SVELoadPredicateRegisterOp { 4154 SVELoadPredicateRegisterFixed = 0x85800000, 4155 SVELoadPredicateRegisterFMask = 0xFFC0E010, 4156 SVELoadPredicateRegisterMask = 0xFFC0E010, 4157 LDR_p_bi = SVELoadPredicateRegisterFixed 4158 }; 4159 4160 enum SVELoadVectorRegisterOp { 4161 SVELoadVectorRegisterFixed = 0x85804000, 4162 SVELoadVectorRegisterFMask = 0xFFC0E000, 4163 SVELoadVectorRegisterMask = 0xFFC0E000, 4164 LDR_z_bi = SVELoadVectorRegisterFixed 4165 }; 4166 4167 enum SVEMulIndexOp { 4168 SVEMulIndexFixed = 0x44200000, 4169 SVEMulIndexFMask = 0xFF200000, 4170 SVEMulIndexMask = 0xFFE0FC00, 4171 SDOT_z_zzzi_s = SVEMulIndexFixed | 0x00800000, 4172 UDOT_z_zzzi_s = SVEMulIndexFixed | 0x00800400, 4173 SDOT_z_zzzi_d = SVEMulIndexFixed | 0x00C00000, 4174 UDOT_z_zzzi_d = SVEMulIndexFixed | 0x00C00400 4175 }; 4176 4177 enum SVEPartitionBreakConditionOp { 4178 SVEPartitionBreakConditionFixed = 0x25104000, 4179 SVEPartitionBreakConditionFMask = 0xFF3FC200, 4180 SVEPartitionBreakConditionMask = 0xFFFFC200, 4181 BRKA_p_p_p = SVEPartitionBreakConditionFixed, 4182 BRKAS_p_p_p_z = SVEPartitionBreakConditionFixed | 0x00400000, 4183 BRKB_p_p_p = SVEPartitionBreakConditionFixed | 0x00800000, 4184 BRKBS_p_p_p_z = SVEPartitionBreakConditionFixed | 0x00C00000 4185 }; 4186 4187 enum SVEPermutePredicateElementsOp { 4188 SVEPermutePredicateElementsFixed = 0x05204000, 4189 SVEPermutePredicateElementsFMask = 0xFF30E210, 4190 SVEPermutePredicateElementsMask = 0xFF30FE10, 4191 ZIP1_p_pp = SVEPermutePredicateElementsFixed, 4192 ZIP2_p_pp = SVEPermutePredicateElementsFixed | 0x00000400, 4193 UZP1_p_pp = SVEPermutePredicateElementsFixed | 0x00000800, 4194 UZP2_p_pp = SVEPermutePredicateElementsFixed | 0x00000C00, 4195 TRN1_p_pp = SVEPermutePredicateElementsFixed | 0x00001000, 4196 TRN2_p_pp = SVEPermutePredicateElementsFixed | 0x00001400 4197 }; 4198 4199 enum SVEPermuteVectorExtractOp { 4200 SVEPermuteVectorExtractFixed = 0x05200000, 4201 SVEPermuteVectorExtractFMask = 0xFF20E000, 4202 SVEPermuteVectorExtractMask = 0xFFE0E000, 4203 EXT_z_zi_des = SVEPermuteVectorExtractFixed 4204 }; 4205 4206 enum SVEPermuteVectorInterleavingOp { 4207 SVEPermuteVectorInterleavingFixed = 0x05206000, 4208 SVEPermuteVectorInterleavingFMask = 0xFF20E000, 4209 SVEPermuteVectorInterleavingMask = 0xFF20FC00, 4210 ZIP1_z_zz = SVEPermuteVectorInterleavingFixed, 4211 ZIP2_z_zz = SVEPermuteVectorInterleavingFixed | 0x00000400, 4212 UZP1_z_zz = SVEPermuteVectorInterleavingFixed | 0x00000800, 4213 UZP2_z_zz = SVEPermuteVectorInterleavingFixed | 0x00000C00, 4214 TRN1_z_zz = SVEPermuteVectorInterleavingFixed | 0x00001000, 4215 TRN2_z_zz = SVEPermuteVectorInterleavingFixed | 0x00001400 4216 }; 4217 4218 enum SVEPredicateCountOp { 4219 SVEPredicateCountFixed = 0x25208000, 4220 SVEPredicateCountFMask = 0xFF38C000, 4221 SVEPredicateCountMask = 0xFF3FC200, 4222 CNTP_r_p_p = SVEPredicateCountFixed 4223 }; 4224 4225 enum SVEPredicateFirstActiveOp { 4226 SVEPredicateFirstActiveFixed = 0x2518C000, 4227 SVEPredicateFirstActiveFMask = 0xFF3FFE10, 4228 SVEPredicateFirstActiveMask = 0xFFFFFE10, 4229 PFIRST_p_p_p = SVEPredicateFirstActiveFixed | 0x00400000 4230 }; 4231 4232 enum SVEPredicateInitializeOp { 4233 SVEPredicateInitializeFixed = 0x2518E000, 4234 SVEPredicateInitializeFMask = 0xFF3EFC10, 4235 SVEPredicateInitializeMask = 0xFF3FFC10, 4236 SVEPredicateInitializeSetFlagsBit = 0x00010000, 4237 PTRUE_p_s = SVEPredicateInitializeFixed | 0x00000000, 4238 PTRUES_p_s = SVEPredicateInitializeFixed | SVEPredicateInitializeSetFlagsBit 4239 }; 4240 4241 enum SVEPredicateLogicalOp { 4242 SVEPredicateLogicalFixed = 0x25004000, 4243 SVEPredicateLogicalFMask = 0xFF30C000, 4244 SVEPredicateLogicalMask = 0xFFF0C210, 4245 SVEPredicateLogicalSetFlagsBit = 0x00400000, 4246 AND_p_p_pp_z = SVEPredicateLogicalFixed, 4247 ANDS_p_p_pp_z = AND_p_p_pp_z | SVEPredicateLogicalSetFlagsBit, 4248 BIC_p_p_pp_z = SVEPredicateLogicalFixed | 0x00000010, 4249 BICS_p_p_pp_z = BIC_p_p_pp_z | SVEPredicateLogicalSetFlagsBit, 4250 EOR_p_p_pp_z = SVEPredicateLogicalFixed | 0x00000200, 4251 EORS_p_p_pp_z = EOR_p_p_pp_z | SVEPredicateLogicalSetFlagsBit, 4252 ORR_p_p_pp_z = SVEPredicateLogicalFixed | 0x00800000, 4253 ORRS_p_p_pp_z = ORR_p_p_pp_z | SVEPredicateLogicalSetFlagsBit, 4254 ORN_p_p_pp_z = SVEPredicateLogicalFixed | 0x00800010, 4255 ORNS_p_p_pp_z = ORN_p_p_pp_z | SVEPredicateLogicalSetFlagsBit, 4256 NAND_p_p_pp_z = SVEPredicateLogicalFixed | 0x00800210, 4257 NANDS_p_p_pp_z = NAND_p_p_pp_z | SVEPredicateLogicalSetFlagsBit, 4258 NOR_p_p_pp_z = SVEPredicateLogicalFixed | 0x00800200, 4259 NORS_p_p_pp_z = NOR_p_p_pp_z | SVEPredicateLogicalSetFlagsBit, 4260 SEL_p_p_pp = SVEPredicateLogicalFixed | 0x00000210 4261 }; 4262 4263 enum SVEPredicateNextActiveOp { 4264 SVEPredicateNextActiveFixed = 0x2519C400, 4265 SVEPredicateNextActiveFMask = 0xFF3FFE10, 4266 SVEPredicateNextActiveMask = 0xFF3FFE10, 4267 PNEXT_p_p_p = SVEPredicateNextActiveFixed 4268 }; 4269 4270 enum SVEPredicateReadFromFFR_PredicatedOp { 4271 SVEPredicateReadFromFFR_PredicatedFixed = 0x2518F000, 4272 SVEPredicateReadFromFFR_PredicatedFMask = 0xFF3FFE10, 4273 SVEPredicateReadFromFFR_PredicatedMask = 0xFFFFFE10, 4274 RDFFR_p_p_f = SVEPredicateReadFromFFR_PredicatedFixed, 4275 RDFFRS_p_p_f = SVEPredicateReadFromFFR_PredicatedFixed | 0x00400000 4276 }; 4277 4278 enum SVEPredicateReadFromFFR_UnpredicatedOp { 4279 SVEPredicateReadFromFFR_UnpredicatedFixed = 0x2519F000, 4280 SVEPredicateReadFromFFR_UnpredicatedFMask = 0xFF3FFFF0, 4281 SVEPredicateReadFromFFR_UnpredicatedMask = 0xFFFFFFF0, 4282 RDFFR_p_f = SVEPredicateReadFromFFR_UnpredicatedFixed 4283 }; 4284 4285 enum SVEPredicateTestOp { 4286 SVEPredicateTestFixed = 0x2510C000, 4287 SVEPredicateTestFMask = 0xFF3FC210, 4288 SVEPredicateTestMask = 0xFFFFC21F, 4289 PTEST_p_p = SVEPredicateTestFixed | 0x00400000 4290 }; 4291 4292 enum SVEPredicateZeroOp { 4293 SVEPredicateZeroFixed = 0x2518E400, 4294 SVEPredicateZeroFMask = 0xFF3FFFF0, 4295 SVEPredicateZeroMask = 0xFFFFFFF0, 4296 PFALSE_p = SVEPredicateZeroFixed 4297 }; 4298 4299 enum SVEPropagateBreakOp { 4300 SVEPropagateBreakFixed = 0x2500C000, 4301 SVEPropagateBreakFMask = 0xFF30C000, 4302 SVEPropagateBreakMask = 0xFFF0C210, 4303 BRKPA_p_p_pp = SVEPropagateBreakFixed, 4304 BRKPB_p_p_pp = SVEPropagateBreakFixed | 0x00000010, 4305 BRKPAS_p_p_pp = SVEPropagateBreakFixed | 0x00400000, 4306 BRKPBS_p_p_pp = SVEPropagateBreakFixed | 0x00400010 4307 }; 4308 4309 enum SVEPropagateBreakToNextPartitionOp { 4310 SVEPropagateBreakToNextPartitionFixed = 0x25184000, 4311 SVEPropagateBreakToNextPartitionFMask = 0xFFBFC210, 4312 SVEPropagateBreakToNextPartitionMask = 0xFFFFC210, 4313 BRKN_p_p_pp = SVEPropagateBreakToNextPartitionFixed, 4314 BRKNS_p_p_pp = SVEPropagateBreakToNextPartitionFixed | 0x00400000 4315 }; 4316 4317 enum SVEReversePredicateElementsOp { 4318 SVEReversePredicateElementsFixed = 0x05344000, 4319 SVEReversePredicateElementsFMask = 0xFF3FFE10, 4320 SVEReversePredicateElementsMask = 0xFF3FFE10, 4321 REV_p_p = SVEReversePredicateElementsFixed 4322 }; 4323 4324 enum SVEReverseVectorElementsOp { 4325 SVEReverseVectorElementsFixed = 0x05383800, 4326 SVEReverseVectorElementsFMask = 0xFF3FFC00, 4327 SVEReverseVectorElementsMask = 0xFF3FFC00, 4328 REV_z_z = SVEReverseVectorElementsFixed 4329 }; 4330 4331 enum SVEReverseWithinElementsOp { 4332 SVEReverseWithinElementsFixed = 0x05248000, 4333 SVEReverseWithinElementsFMask = 0xFF3CE000, 4334 SVEReverseWithinElementsMask = 0xFF3FE000, 4335 REVB_z_z = SVEReverseWithinElementsFixed, 4336 REVH_z_z = SVEReverseWithinElementsFixed | 0x00010000, 4337 REVW_z_z = SVEReverseWithinElementsFixed | 0x00020000, 4338 RBIT_z_p_z = SVEReverseWithinElementsFixed | 0x00030000 4339 }; 4340 4341 enum SVESaturatingIncDecRegisterByElementCountOp { 4342 SVESaturatingIncDecRegisterByElementCountFixed = 0x0420F000, 4343 SVESaturatingIncDecRegisterByElementCountFMask = 0xFF20F000, 4344 SVESaturatingIncDecRegisterByElementCountMask = 0xFFF0FC00, 4345 SQINCB_r_rs_sx = SVESaturatingIncDecRegisterByElementCountFixed, 4346 UQINCB_r_rs_uw = SVESaturatingIncDecRegisterByElementCountFixed | 0x00000400, 4347 SQDECB_r_rs_sx = SVESaturatingIncDecRegisterByElementCountFixed | 0x00000800, 4348 UQDECB_r_rs_uw = SVESaturatingIncDecRegisterByElementCountFixed | 0x00000C00, 4349 SQINCB_r_rs_x = SVESaturatingIncDecRegisterByElementCountFixed | 0x00100000, 4350 UQINCB_r_rs_x = SVESaturatingIncDecRegisterByElementCountFixed | 0x00100400, 4351 SQDECB_r_rs_x = SVESaturatingIncDecRegisterByElementCountFixed | 0x00100800, 4352 UQDECB_r_rs_x = SVESaturatingIncDecRegisterByElementCountFixed | 0x00100C00, 4353 SQINCH_r_rs_sx = SVESaturatingIncDecRegisterByElementCountFixed | 0x00400000, 4354 UQINCH_r_rs_uw = SVESaturatingIncDecRegisterByElementCountFixed | 0x00400400, 4355 SQDECH_r_rs_sx = SVESaturatingIncDecRegisterByElementCountFixed | 0x00400800, 4356 UQDECH_r_rs_uw = SVESaturatingIncDecRegisterByElementCountFixed | 0x00400C00, 4357 SQINCH_r_rs_x = SVESaturatingIncDecRegisterByElementCountFixed | 0x00500000, 4358 UQINCH_r_rs_x = SVESaturatingIncDecRegisterByElementCountFixed | 0x00500400, 4359 SQDECH_r_rs_x = SVESaturatingIncDecRegisterByElementCountFixed | 0x00500800, 4360 UQDECH_r_rs_x = SVESaturatingIncDecRegisterByElementCountFixed | 0x00500C00, 4361 SQINCW_r_rs_sx = SVESaturatingIncDecRegisterByElementCountFixed | 0x00800000, 4362 UQINCW_r_rs_uw = SVESaturatingIncDecRegisterByElementCountFixed | 0x00800400, 4363 SQDECW_r_rs_sx = SVESaturatingIncDecRegisterByElementCountFixed | 0x00800800, 4364 UQDECW_r_rs_uw = SVESaturatingIncDecRegisterByElementCountFixed | 0x00800C00, 4365 SQINCW_r_rs_x = SVESaturatingIncDecRegisterByElementCountFixed | 0x00900000, 4366 UQINCW_r_rs_x = SVESaturatingIncDecRegisterByElementCountFixed | 0x00900400, 4367 SQDECW_r_rs_x = SVESaturatingIncDecRegisterByElementCountFixed | 0x00900800, 4368 UQDECW_r_rs_x = SVESaturatingIncDecRegisterByElementCountFixed | 0x00900C00, 4369 SQINCD_r_rs_sx = SVESaturatingIncDecRegisterByElementCountFixed | 0x00C00000, 4370 UQINCD_r_rs_uw = SVESaturatingIncDecRegisterByElementCountFixed | 0x00C00400, 4371 SQDECD_r_rs_sx = SVESaturatingIncDecRegisterByElementCountFixed | 0x00C00800, 4372 UQDECD_r_rs_uw = SVESaturatingIncDecRegisterByElementCountFixed | 0x00C00C00, 4373 SQINCD_r_rs_x = SVESaturatingIncDecRegisterByElementCountFixed | 0x00D00000, 4374 UQINCD_r_rs_x = SVESaturatingIncDecRegisterByElementCountFixed | 0x00D00400, 4375 SQDECD_r_rs_x = SVESaturatingIncDecRegisterByElementCountFixed | 0x00D00800, 4376 UQDECD_r_rs_x = SVESaturatingIncDecRegisterByElementCountFixed | 0x00D00C00 4377 }; 4378 4379 enum SVESaturatingIncDecVectorByElementCountOp { 4380 SVESaturatingIncDecVectorByElementCountFixed = 0x0420C000, 4381 SVESaturatingIncDecVectorByElementCountFMask = 0xFF30F000, 4382 SVESaturatingIncDecVectorByElementCountMask = 0xFFF0FC00, 4383 SQINCH_z_zs = SVESaturatingIncDecVectorByElementCountFixed | 0x00400000, 4384 UQINCH_z_zs = SVESaturatingIncDecVectorByElementCountFixed | 0x00400400, 4385 SQDECH_z_zs = SVESaturatingIncDecVectorByElementCountFixed | 0x00400800, 4386 UQDECH_z_zs = SVESaturatingIncDecVectorByElementCountFixed | 0x00400C00, 4387 SQINCW_z_zs = SVESaturatingIncDecVectorByElementCountFixed | 0x00800000, 4388 UQINCW_z_zs = SVESaturatingIncDecVectorByElementCountFixed | 0x00800400, 4389 SQDECW_z_zs = SVESaturatingIncDecVectorByElementCountFixed | 0x00800800, 4390 UQDECW_z_zs = SVESaturatingIncDecVectorByElementCountFixed | 0x00800C00, 4391 SQINCD_z_zs = SVESaturatingIncDecVectorByElementCountFixed | 0x00C00000, 4392 UQINCD_z_zs = SVESaturatingIncDecVectorByElementCountFixed | 0x00C00400, 4393 SQDECD_z_zs = SVESaturatingIncDecVectorByElementCountFixed | 0x00C00800, 4394 UQDECD_z_zs = SVESaturatingIncDecVectorByElementCountFixed | 0x00C00C00 4395 }; 4396 4397 enum SVEStackFrameAdjustmentOp { 4398 SVEStackFrameAdjustmentFixed = 0x04205000, 4399 SVEStackFrameAdjustmentFMask = 0xFFA0F800, 4400 SVEStackFrameAdjustmentMask = 0xFFE0F800, 4401 ADDVL_r_ri = SVEStackFrameAdjustmentFixed, 4402 ADDPL_r_ri = SVEStackFrameAdjustmentFixed | 0x00400000 4403 }; 4404 4405 enum SVEStackFrameSizeOp { 4406 SVEStackFrameSizeFixed = 0x04BF5000, 4407 SVEStackFrameSizeFMask = 0xFFFFF800, 4408 SVEStackFrameSizeMask = 0xFFFFF800, 4409 RDVL_r_i = SVEStackFrameSizeFixed 4410 }; 4411 4412 enum SVEStoreMultipleStructures_ScalarPlusImmOp { 4413 SVEStoreMultipleStructures_ScalarPlusImmFixed = 0xE410E000, 4414 SVEStoreMultipleStructures_ScalarPlusImmFMask = 0xFE10E000, 4415 SVEStoreMultipleStructures_ScalarPlusImmMask = 0xFFF0E000, 4416 ST2B_z_p_bi_contiguous = SVEStoreMultipleStructures_ScalarPlusImmFixed | 0x00200000, 4417 ST3B_z_p_bi_contiguous = SVEStoreMultipleStructures_ScalarPlusImmFixed | 0x00400000, 4418 ST4B_z_p_bi_contiguous = SVEStoreMultipleStructures_ScalarPlusImmFixed | 0x00600000, 4419 ST2H_z_p_bi_contiguous = SVEStoreMultipleStructures_ScalarPlusImmFixed | 0x00A00000, 4420 ST3H_z_p_bi_contiguous = SVEStoreMultipleStructures_ScalarPlusImmFixed | 0x00C00000, 4421 ST4H_z_p_bi_contiguous = SVEStoreMultipleStructures_ScalarPlusImmFixed | 0x00E00000, 4422 ST2W_z_p_bi_contiguous = SVEStoreMultipleStructures_ScalarPlusImmFixed | 0x01200000, 4423 ST3W_z_p_bi_contiguous = SVEStoreMultipleStructures_ScalarPlusImmFixed | 0x01400000, 4424 ST4W_z_p_bi_contiguous = SVEStoreMultipleStructures_ScalarPlusImmFixed | 0x01600000, 4425 ST2D_z_p_bi_contiguous = SVEStoreMultipleStructures_ScalarPlusImmFixed | 0x01A00000, 4426 ST3D_z_p_bi_contiguous = SVEStoreMultipleStructures_ScalarPlusImmFixed | 0x01C00000, 4427 ST4D_z_p_bi_contiguous = SVEStoreMultipleStructures_ScalarPlusImmFixed | 0x01E00000 4428 }; 4429 4430 enum SVEStoreMultipleStructures_ScalarPlusScalarOp { 4431 SVEStoreMultipleStructures_ScalarPlusScalarFixed = 0xE4006000, 4432 SVEStoreMultipleStructures_ScalarPlusScalarFMask = 0xFE00E000, 4433 SVEStoreMultipleStructures_ScalarPlusScalarMask = 0xFFE0E000, 4434 ST2B_z_p_br_contiguous = SVEStoreMultipleStructures_ScalarPlusScalarFixed | 0x00200000, 4435 ST3B_z_p_br_contiguous = SVEStoreMultipleStructures_ScalarPlusScalarFixed | 0x00400000, 4436 ST4B_z_p_br_contiguous = SVEStoreMultipleStructures_ScalarPlusScalarFixed | 0x00600000, 4437 ST2H_z_p_br_contiguous = SVEStoreMultipleStructures_ScalarPlusScalarFixed | 0x00A00000, 4438 ST3H_z_p_br_contiguous = SVEStoreMultipleStructures_ScalarPlusScalarFixed | 0x00C00000, 4439 ST4H_z_p_br_contiguous = SVEStoreMultipleStructures_ScalarPlusScalarFixed | 0x00E00000, 4440 ST2W_z_p_br_contiguous = SVEStoreMultipleStructures_ScalarPlusScalarFixed | 0x01200000, 4441 ST3W_z_p_br_contiguous = SVEStoreMultipleStructures_ScalarPlusScalarFixed | 0x01400000, 4442 ST4W_z_p_br_contiguous = SVEStoreMultipleStructures_ScalarPlusScalarFixed | 0x01600000, 4443 ST2D_z_p_br_contiguous = SVEStoreMultipleStructures_ScalarPlusScalarFixed | 0x01A00000, 4444 ST3D_z_p_br_contiguous = SVEStoreMultipleStructures_ScalarPlusScalarFixed | 0x01C00000, 4445 ST4D_z_p_br_contiguous = SVEStoreMultipleStructures_ScalarPlusScalarFixed | 0x01E00000 4446 }; 4447 4448 enum SVEStorePredicateRegisterOp { 4449 SVEStorePredicateRegisterFixed = 0xE5800000, 4450 SVEStorePredicateRegisterFMask = 0xFFC0E010, 4451 SVEStorePredicateRegisterMask = 0xFFC0E010, 4452 STR_p_bi = SVEStorePredicateRegisterFixed 4453 }; 4454 4455 enum SVEStoreVectorRegisterOp { 4456 SVEStoreVectorRegisterFixed = 0xE5804000, 4457 SVEStoreVectorRegisterFMask = 0xFFC0E000, 4458 SVEStoreVectorRegisterMask = 0xFFC0E000, 4459 STR_z_bi = SVEStoreVectorRegisterFixed 4460 }; 4461 4462 enum SVETableLookupOp { 4463 SVETableLookupFixed = 0x05203000, 4464 SVETableLookupFMask = 0xFF20FC00, 4465 SVETableLookupMask = 0xFF20FC00, 4466 TBL_z_zz_1 = SVETableLookupFixed 4467 }; 4468 4469 enum SVEUnpackPredicateElementsOp { 4470 SVEUnpackPredicateElementsFixed = 0x05304000, 4471 SVEUnpackPredicateElementsFMask = 0xFFFEFE10, 4472 SVEUnpackPredicateElementsMask = 0xFFFFFE10, 4473 PUNPKLO_p_p = SVEUnpackPredicateElementsFixed, 4474 PUNPKHI_p_p = SVEUnpackPredicateElementsFixed | 0x00010000 4475 }; 4476 4477 enum SVEUnpackVectorElementsOp { 4478 SVEUnpackVectorElementsFixed = 0x05303800, 4479 SVEUnpackVectorElementsFMask = 0xFF3CFC00, 4480 SVEUnpackVectorElementsMask = 0xFF3FFC00, 4481 SUNPKLO_z_z = SVEUnpackVectorElementsFixed, 4482 SUNPKHI_z_z = SVEUnpackVectorElementsFixed | 0x00010000, 4483 UUNPKLO_z_z = SVEUnpackVectorElementsFixed | 0x00020000, 4484 UUNPKHI_z_z = SVEUnpackVectorElementsFixed | 0x00030000 4485 }; 4486 4487 enum SVEVectorSelectOp { 4488 SVEVectorSelectFixed = 0x0520C000, 4489 SVEVectorSelectFMask = 0xFF20C000, 4490 SVEVectorSelectMask = 0xFF20C000, 4491 SEL_z_p_zz = SVEVectorSelectFixed 4492 }; 4493 4494 enum SVEVectorSpliceOp { 4495 SVEVectorSpliceFixed = 0x052C8000, 4496 SVEVectorSpliceFMask = 0xFF3FE000, 4497 SVEVectorSpliceMask = 0xFF3FE000, 4498 SPLICE_z_p_zz_des = SVEVectorSpliceFixed 4499 }; 4500 4501 enum ReservedOp : uint32_t { 4502 ReservedFixed = 0x00000000, 4503 ReservedFMask = 0x1E000000, 4504 ReservedMask = 0xFFFF0000, 4505 UDF = ReservedFixed | 0x00000000 4506 }; 4507 4508 // Unimplemented and unallocated instructions. These are defined to make fixed 4509 // bit assertion easier. 4510 enum UnimplementedOp : uint32_t { 4511 UnimplementedFixed = 0x00000000, 4512 UnimplementedFMask = 0x00000000 4513 }; 4514 4515 enum UnallocatedOp : uint32_t { 4516 UnallocatedFixed = 0x00000000, 4517 UnallocatedFMask = 0x00000000 4518 }; 4519 4520 // Mozilla change: Add enum for CSSC max-min immediate instructions 4521 enum MaxMinImmediateOp : uint32_t { 4522 MaxMinImmediateFixed = 0x11C00000, 4523 MaxMinImmediateFMask = 0x1FC00000, 4524 MaxMinImmediateMask = 0xFFFC0000, 4525 SMAX_imm = MaxMinImmediateFixed | 0x0000'0000, 4526 SMAX_w_imm = SMAX_imm, 4527 SMAX_x_imm = SMAX_imm | SixtyFourBits, 4528 SMIN_imm = MaxMinImmediateFixed | 0x0008'0000, 4529 SMIN_w_imm = SMIN_imm, 4530 SMIN_x_imm = SMIN_imm | SixtyFourBits, 4531 UMAX_imm = MaxMinImmediateFixed | 0x0004'0000, 4532 UMAX_w_imm = UMAX_imm, 4533 UMAX_x_imm = UMAX_imm | SixtyFourBits, 4534 UMIN_imm = MaxMinImmediateFixed | 0x000c'0000, 4535 UMIN_w_imm = UMIN_imm, 4536 UMIN_x_imm = UMIN_imm | SixtyFourBits, 4537 }; 4538 4539 // Re-enable `clang-format` after the `enum`s. 4540 // clang-format on 4541 4542 // Mozilla change: 4543 // 4544 // Instruction bit pattern for an undefined instruction, that will trigger a 4545 // SIGILL at runtime. 4546 // 4547 // A couple of strategies we can use here. There are no unencoded 4548 // instructions in the instruction set that are guaranteed to remain that 4549 // way. However there are some currently (as of 2018) unencoded 4550 // instructions that are good candidates. 4551 // 4552 // Ideally, unencoded instructions should be non-destructive to the register 4553 // state, and should be unencoded at all exception levels. 4554 // 4555 // At the trap the pc will hold the address of the offending instruction. 4556 // 4557 // Some candidates for unencoded instructions: 4558 // 4559 // 0xd4a00000 (essentially dcps0, a good one since it is nonsensical and may 4560 // remain unencoded in the future for that reason) 4561 // 0x33000000 (bfm variant) 4562 // 0xd67f0000 (br variant) 4563 // 0x5ac00c00 (rbit variant) 4564 // 4565 // This instruction is "dcps0", also has 16-bit payload if needed. 4566 static constexpr uint32_t UNDEFINED_INST_PATTERN = DCPS0; 4567 4568 } // namespace vixl 4569 4570 #endif // VIXL_A64_CONSTANTS_A64_H_