tor-browser

commit 8b0fe0242404df25797bbd36fadbcf8e91910b4b
parent f7b0e6cbcfaadb50000e1401777ca98a8b40105b
Author: André Bargull <andre.bargull@gmail.com>
Date:   Thu, 23 Oct 2025 10:11:48 +0000

Bug 1995561 - Part 2: Explicitly allocate Int64 registers in arm32-specific lowering. r=spidermonkey-reviewers,iain

Be explicit that Int64 registers are allocated, so that readers don't need to
remember that `LIRGeneratorShared::useInt64` always allocates registers for
Int64 uses on 32-bit platforms.

Differential Revision: https://phabricator.services.mozilla.com/D269412

Diffstat:
M
js/src/jit/arm/Lowering-arm.cpp
 | 
6
+++---

1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/js/src/jit/arm/Lowering-arm.cpp b/js/src/jit/arm/Lowering-arm.cpp
@@ -195,7 +195,7 @@ void LIRGeneratorARM::lowerForALUInt64(
     LInstructionHelper<INT64_PIECES, 2 * INT64_PIECES, 0>* ins,
     MDefinition* mir, MDefinition* lhs, MDefinition* rhs) {
   ins->setInt64Operand(0, useInt64RegisterAtStart(lhs));
-  ins->setInt64Operand(INT64_PIECES, useInt64OrConstant(rhs));
+  ins->setInt64Operand(INT64_PIECES, useInt64RegisterOrConstant(rhs));
   defineInt64ReuseInput(ins, mir, 0);
 }
 
@@ -216,7 +216,7 @@ void LIRGeneratorARM::lowerForMulInt64(LMulI64* ins, MMul* mir,
   }
 
   ins->setLhs(useInt64RegisterAtStart(lhs));
-  ins->setRhs(useInt64OrConstant(rhs));
+  ins->setRhs(useInt64RegisterOrConstant(rhs));
   if (needsTemp) {
     ins->setTemp0(temp());
   }
@@ -506,7 +506,7 @@ void LIRGeneratorARM::lowerWasmSelectI(MWasmSelect* select) {
 void LIRGeneratorARM::lowerWasmSelectI64(MWasmSelect* select) {
   auto* lir = new (alloc()) LWasmSelectI64(
       useInt64RegisterAtStart(select->trueExpr()),
-      useInt64(select->falseExpr()), useRegister(select->condExpr()));
+      useInt64Register(select->falseExpr()), useRegister(select->condExpr()));
   defineInt64ReuseInput(lir, select, LWasmSelectI64::TrueExprIndex);
 }