tor-browser

commit f7b0e6cbcfaadb50000e1401777ca98a8b40105b
parent 5378a419d8c1fcb760b7da1e2b9c0aa81c67266d
Author: André Bargull <andre.bargull@gmail.com>
Date:   Thu, 23 Oct 2025 10:11:48 +0000

Bug 1995561 - Part 1: Remove ToOperandOrRegister64 from arm32. r=spidermonkey-reviewers,iain

Inline `ToOperandOrRegister64` and directly call `ToRegister64`.

Differential Revision: https://phabricator.services.mozilla.com/D269411

Diffstat:
M
js/src/jit/arm/CodeGenerator-arm.cpp
 | 
17
++++++-----------
M
js/src/jit/arm/CodeGenerator-arm.h
 | 
2
--

2 files changed, 6 insertions(+), 13 deletions(-)
diff --git a/js/src/jit/arm/CodeGenerator-arm.cpp b/js/src/jit/arm/CodeGenerator-arm.cpp
@@ -45,11 +45,6 @@ CodeGeneratorARM::CodeGeneratorARM(MIRGenerator* gen, LIRGraph* graph,
                                    const wasm::CodeMetadata* wasmCodeMeta)
     : CodeGeneratorShared(gen, graph, masm, wasmCodeMeta) {}
 
-Register64 CodeGeneratorARM::ToOperandOrRegister64(
-    const LInt64Allocation& input) {
-  return ToRegister64(input);
-}
-
 void CodeGeneratorARM::emitBranch(Assembler::Condition cond,
                                   MBasicBlock* mirTrue, MBasicBlock* mirFalse) {
   if (isNextBlock(mirFalse->lir())) {
@@ -201,7 +196,7 @@ void CodeGenerator::visitAddI64(LAddI64* lir) {
     return;
   }
 
-  masm.add64(ToOperandOrRegister64(rhs), ToRegister64(lhs));
+  masm.add64(ToRegister64(rhs), ToRegister64(lhs));
 }
 
 void CodeGenerator::visitSubI(LSubI* ins) {
@@ -255,7 +250,7 @@ void CodeGenerator::visitSubI64(LSubI64* lir) {
     return;
   }
 
-  masm.sub64(ToOperandOrRegister64(rhs), ToRegister64(lhs));
+  masm.sub64(ToRegister64(rhs), ToRegister64(lhs));
 }
 
 void CodeGenerator::visitMulI(LMulI* ins) {
@@ -460,7 +455,7 @@ void CodeGenerator::visitMulI64(LMulI64* lir) {
     }
   } else {
     Register temp = ToTempRegisterOrInvalid(lir->temp0());
-    masm.mul64(ToOperandOrRegister64(rhs), ToRegister64(lhs), temp);
+    masm.mul64(ToRegister64(rhs), ToRegister64(lhs), temp);
   }
 }
 
@@ -2570,21 +2565,21 @@ void CodeGenerator::visitBitOpI64(LBitOpI64* lir) {
       if (IsConstant(rhs)) {
         masm.or64(Imm64(ToInt64(rhs)), ToRegister64(lhs));
       } else {
-        masm.or64(ToOperandOrRegister64(rhs), ToRegister64(lhs));
+        masm.or64(ToRegister64(rhs), ToRegister64(lhs));
       }
       break;
     case JSOp::BitXor:
       if (IsConstant(rhs)) {
         masm.xor64(Imm64(ToInt64(rhs)), ToRegister64(lhs));
       } else {
-        masm.xor64(ToOperandOrRegister64(rhs), ToRegister64(lhs));
+        masm.xor64(ToRegister64(rhs), ToRegister64(lhs));
       }
       break;
     case JSOp::BitAnd:
       if (IsConstant(rhs)) {
         masm.and64(Imm64(ToInt64(rhs)), ToRegister64(lhs));
       } else {
-        masm.and64(ToOperandOrRegister64(rhs), ToRegister64(lhs));
+        masm.and64(ToRegister64(rhs), ToRegister64(lhs));
       }
       break;
     default:
diff --git a/js/src/jit/arm/CodeGenerator-arm.h b/js/src/jit/arm/CodeGenerator-arm.h
@@ -91,8 +91,6 @@ class CodeGeneratorARM : public CodeGeneratorShared {
   template <typename T>
   void emitWasmUnalignedStore(T* ins);
 
-  Register64 ToOperandOrRegister64(const LInt64Allocation& input);
-
   void divICommon(MDiv* mir, Register lhs, Register rhs, Register output,
                   LSnapshot* snapshot, Label& done);
   void modICommon(MMod* mir, Register lhs, Register rhs, Register output,