tor-browser

commit 4440019a1572ce976ab2ae4052c5a0df4484c99e
parent 7ee3625ee3bea342ef4b85ba2b6910f5cfd4e6d3
Author: André Bargull <andre.bargull@gmail.com>
Date:   Fri, 17 Oct 2025 11:25:43 +0000

Bug 1992993 - Part 9: Avoid vanilla allocation warnings for riscv64. r=spidermonkey-reviewers,iain

"config/check_vanilla_allocations.py" complains about allocations for
`std::vector` and `std::string`. Rewrite to use non-allocating alternatives
resp. to use `js::Vector`.

Differential Revision: https://phabricator.services.mozilla.com/D267797

Diffstat:
M
js/src/jit/riscv64/Simulator-riscv64.h
 | 
26
+++++++++++++++++++++++++-
M
js/src/jit/riscv64/disasm/Disasm-riscv64.cpp
 | 
22
++++++++++++----------

2 files changed, 37 insertions(+), 11 deletions(-)
diff --git a/js/src/jit/riscv64/Simulator-riscv64.h b/js/src/jit/riscv64/Simulator-riscv64.h
@@ -40,6 +40,8 @@
 #  include "jit/riscv64/constant/util-riscv64.h"
 #  include "jit/riscv64/disasm/Disasm-riscv64.h"
 #  include "js/ProfilingFrameIterator.h"
+#  include "js/Utility.h"
+#  include "js/Vector.h"
 #  include "threading/Thread.h"
 #  include "vm/MutexIDs.h"
 #  include "wasm/WasmSignalHandlers.h"
@@ -386,6 +388,28 @@ class SimInstruction : public InstructionGetters<SimInstructionBase> {
   }
 };
 
+// std::vector shim for breakpoints
+template <typename T>
+class BreakpointVector final {
+  js::Vector<T, 0, js::SystemAllocPolicy> vector_;
+
+ public:
+  BreakpointVector() = default;
+
+  size_t size() const { return vector_.length(); }
+
+  T& at(size_t i) { return vector_[i]; }
+  const T& at(size_t i) const { return vector_[i]; }
+
+  template <typename U>
+  void push_back(U&& u) {
+    js::AutoEnterOOMUnsafeRegion oomUnsafe;
+    if (!vector_.emplaceBack(std::move(u))) {
+      oomUnsafe.crash("breakpoint vector push_back");
+    }
+  }
+};
+
 // Per thread simulator state.
 class Simulator {
   friend class RiscvDebugger;
@@ -993,7 +1017,7 @@ class Simulator {
     bool enabled;
     bool is_tbreak;
   };
-  std::vector<Breakpoint> breakpoints_;
+  BreakpointVector<Breakpoint> breakpoints_;
   void SetBreakpoint(SimInstruction* breakpoint, bool is_tbreak);
   void ListBreakpoints();
   void CheckBreakpoints();
diff --git a/js/src/jit/riscv64/disasm/Disasm-riscv64.cpp b/js/src/jit/riscv64/disasm/Disasm-riscv64.cpp
@@ -30,6 +30,7 @@
 #include <stdarg.h>
 #include <stdio.h>
 #include <string.h>
+#include <string_view>
 
 #include "jit/riscv64/Assembler-riscv64.h"
 
@@ -843,7 +844,7 @@ void Decoder::PrintAcquireRelease(Instruction* instr) {
 
 void Decoder::PrintCSRReg(Instruction* instr) {
   int32_t csr_reg = instr->CsrValue();
-  std::string s;
+  std::string_view s;
   switch (csr_reg) {
     case csr_fflags:  // Floating-Point Accrued Exceptions (RW)
       s = "csr_fflags";
@@ -875,12 +876,12 @@ void Decoder::PrintCSRReg(Instruction* instr) {
     default:
       MOZ_CRASH();
   }
-  out_buffer_pos_ += SNPrintF(out_buffer_ + out_buffer_pos_, "%s", s.c_str());
+  out_buffer_pos_ += SNPrintF(out_buffer_ + out_buffer_pos_, "%s", s.data());
 }
 
 void Decoder::PrintRoundingMode(Instruction* instr) {
   int frm = instr->RoundMode();
-  std::string s;
+  std::string_view s;
   switch (frm) {
     case RNE:
       s = "RNE";
@@ -903,25 +904,26 @@ void Decoder::PrintRoundingMode(Instruction* instr) {
     default:
       MOZ_CRASH();
   }
-  out_buffer_pos_ += SNPrintF(out_buffer_ + out_buffer_pos_, "%s", s.c_str());
+  out_buffer_pos_ += SNPrintF(out_buffer_ + out_buffer_pos_, "%s", s.data());
 }
 
 void Decoder::PrintMemoryOrder(Instruction* instr, bool is_pred) {
   int memOrder = instr->MemoryOrder(is_pred);
-  std::string s;
+  char s[5] = {};
+  char* ps = s;
   if ((memOrder & PSI) == PSI) {
-    s += "i";
+    *ps++ = 'i';
   }
   if ((memOrder & PSO) == PSO) {
-    s += "o";
+    *ps++ = 'o';
   }
   if ((memOrder & PSR) == PSR) {
-    s += "r";
+    *ps++ = 'r';
   }
   if ((memOrder & PSW) == PSW) {
-    s += "w";
+    *ps++ = 'w';
   }
-  out_buffer_pos_ += SNPrintF(out_buffer_ + out_buffer_pos_, "%s", s.c_str());
+  out_buffer_pos_ += SNPrintF(out_buffer_ + out_buffer_pos_, "%s", s);
 }
 
 // Printing of instruction name.