tor-browser

commit 19605c67c4ff06e4b4904c1a919a289b8dcc3647
parent 59b1aeddea9831a6ce84c661079320c4a49f08e1
Author: André Bargull <andre.bargull@gmail.com>
Date:   Wed, 17 Dec 2025 13:42:06 +0000

Bug 2002522 - Part 3: Fix deprecated enum-enum conversion warnings for arm64. r=spidermonkey-reviewers,jandem

Add explicit casts to squelch deprecated-enum-enum-conversion warnings.

Also see bug 1791955.

Differential Revision: https://phabricator.services.mozilla.com/D274123

Diffstat:
M
js/src/jit/arm64/vixl/Assembler-vixl.cpp
 | 
12
++++++------
M
js/src/jit/arm64/vixl/Constants-vixl.h
 | 
10
++++++----
M
js/src/jit/arm64/vixl/Instructions-vixl.h
 | 
2
+-
M
js/src/jit/arm64/vixl/MozAssembler-vixl.cpp
 | 
2
+-

4 files changed, 14 insertions(+), 12 deletions(-)
diff --git a/js/src/jit/arm64/vixl/Assembler-vixl.cpp b/js/src/jit/arm64/vixl/Assembler-vixl.cpp
@@ -785,7 +785,7 @@ void Assembler::LoadStorePairNonTemporal(const CPURegister& rt,
   VIXL_ASSERT(addr.IsImmediateOffset());
 
   unsigned size = CalcLSPairDataSize(
-    static_cast<LoadStorePairOp>(op & LoadStorePairMask));
+    static_cast<LoadStorePairOp>(static_cast<Instr>(op) & LoadStorePairMask));
   VIXL_ASSERT(IsImmLSPair(addr.offset(), size));
   int offset = static_cast<int>(addr.offset());
   Emit(op | Rt(rt) | Rt2(rt2) | RnSP(addr.base()) | ImmLSPair(offset, size));
@@ -4053,13 +4053,13 @@ void Assembler::AddSub(const Register& rd,
     if (rn.IsSP() || rd.IsSP()) {
       VIXL_ASSERT(!(rd.IsSP() && (S == SetFlags)));
       DataProcExtendedRegister(rd, rn, operand.ToExtendedRegister(), S,
-                               AddSubExtendedFixed | op);
+                               AddSubExtendedFixed | static_cast<Instr>(op));
     } else {
-      DataProcShiftedRegister(rd, rn, operand, S, AddSubShiftedFixed | op);
+      DataProcShiftedRegister(rd, rn, operand, S, AddSubShiftedFixed | static_cast<Instr>(op));
     }
   } else {
     VIXL_ASSERT(operand.IsExtendedRegister());
-    DataProcExtendedRegister(rd, rn, operand, S, AddSubExtendedFixed | op);
+    DataProcExtendedRegister(rd, rn, operand, S, AddSubExtendedFixed | static_cast<Instr>(op));
   }
 }
 
@@ -4102,11 +4102,11 @@ void Assembler::ConditionalCompare(const Register& rn,
   if (operand.IsImmediate()) {
     int64_t immediate = operand.immediate();
     VIXL_ASSERT(IsImmConditionalCompare(immediate));
-    ccmpop = ConditionalCompareImmediateFixed | op |
+    ccmpop = ConditionalCompareImmediateFixed | static_cast<Instr>(op) |
         ImmCondCmp(static_cast<unsigned>(immediate));
   } else {
     VIXL_ASSERT(operand.IsShiftedRegister() && (operand.shift_amount() == 0));
-    ccmpop = ConditionalCompareRegisterFixed | op | Rm(operand.reg());
+    ccmpop = ConditionalCompareRegisterFixed | static_cast<Instr>(op) | Rm(operand.reg());
   }
   Emit(SF(rn) | ccmpop | Cond(cond) | Rn(rn) | Nzcv(nzcv));
 }
diff --git a/js/src/jit/arm64/vixl/Constants-vixl.h b/js/src/jit/arm64/vixl/Constants-vixl.h
@@ -632,7 +632,8 @@ enum SVEPredicateConstraint {
 
 
 // Generic fields.
-enum GenericInstrField : uint32_t {
+using GenericInstrField = uint32_t;
+constexpr GenericInstrField
   SixtyFourBits        = 0x80000000,
   ThirtyTwoBits        = 0x00000000,
 
@@ -640,9 +641,10 @@ enum GenericInstrField : uint32_t {
   FP16                 = 0x00C00000,
   FP32                 = 0x00000000,
   FP64                 = 0x00400000
-};
+;
 
-enum NEONFormatField : uint32_t {
+using NEONFormatField = uint32_t;
+constexpr NEONFormatField
   NEONFormatFieldMask   = 0x40C00000,
   NEON_Q                = 0x40000000,
   NEON_8B               = 0x00000000,
@@ -653,7 +655,7 @@ enum NEONFormatField : uint32_t {
   NEON_4S               = NEON_2S | NEON_Q,
   NEON_1D               = 0x00C00000,
   NEON_2D               = 0x00C00000 | NEON_Q
-};
+;
 
 enum NEONFPFormatField : uint32_t {
   NEONFPFormatFieldMask = 0x40400000,
diff --git a/js/src/jit/arm64/vixl/Instructions-vixl.h b/js/src/jit/arm64/vixl/Instructions-vixl.h
@@ -687,7 +687,7 @@ class Instruction {
       // can set the flags. The others can all write into sp.
       // Note that some logical operations are not available to
       // immediate-operand instructions, so we have to combine two masks here.
-      if (Mask(LogicalImmediateMask & LogicalOpMask) == ANDS) {
+      if (Mask(static_cast<Instr>(LogicalImmediateMask) & LogicalOpMask) == ANDS) {
         return Reg31IsZeroRegister;
       } else {
         return Reg31IsStackPointer;
diff --git a/js/src/jit/arm64/vixl/MozAssembler-vixl.cpp b/js/src/jit/arm64/vixl/MozAssembler-vixl.cpp
@@ -444,7 +444,7 @@ BufferOffset Assembler::Logical(const Register& rd, const Register& rn,
   } else {
     VIXL_ASSERT(operand.IsShiftedRegister());
     VIXL_ASSERT(operand.reg().size() == rd.size());
-    Instr dp_op = static_cast<Instr>(op | LogicalShiftedFixed);
+    Instr dp_op = static_cast<Instr>(static_cast<Instr>(op) | LogicalShiftedFixed);
     return DataProcShiftedRegister(rd, rn, operand, LeaveFlags, dp_op);
   }
 }