tor-browser

commit fadf320e1749ba3c29f1c29e28ec74686e9fd2ef
parent bba78a6469c9c8563a2f480e182dfcbaa080eaf6
Author: Rong "Mantle" Bao <webmaster@csmantle.top>
Date:   Thu, 27 Nov 2025 11:57:06 +0000

Bug 1996840 - Part 5: (Drive-by) Update used archs in SMDOC for AssemblerBufferWithConstantPools. r=nbp

MIPS is no longer using AssemblerBufferWithConstantPools while RISCV64
is currently using it, according to
<https://searchfox.org/firefox-main/search?q=AssemblerBufferWithConstantPools&path=&case=true&regexp=false>.

Differential Revision: https://phabricator.services.mozilla.com/D270943

Diffstat:
M
js/src/jit/shared/IonAssemblerBufferWithConstantPools.h
 | 
8
++++----

1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/js/src/jit/shared/IonAssemblerBufferWithConstantPools.h b/js/src/jit/shared/IonAssemblerBufferWithConstantPools.h
@@ -15,7 +15,7 @@
 #include "jit/JitSpewer.h"
 #include "jit/shared/IonAssemblerBuffer.h"
 
-// [SMDOC] JIT AssemblerBuffer constant pooling (ARM/ARM64/MIPS)
+// [SMDOC] JIT AssemblerBuffer constant pooling (ARM/ARM64/RISCV64)
 //
 // This code extends the AssemblerBuffer to support the pooling of values loaded
 // using program-counter relative addressing modes. This is necessary with the
@@ -69,9 +69,9 @@
 // leaveNoPool().
 
 // The only planned instruction sets that require inline constant pools are the
-// ARM, ARM64, and MIPS, and these all have fixed 32-bit sized instructions so
-// for simplicity the code below is specialized for fixed 32-bit sized
-// instructions and makes no attempt to support variable length
+// ARM, ARM64, RISCV64 (and historically MIPS), and these all have fixed 32-bit
+// sized instructions so for simplicity the code below is specialized for fixed
+// 32-bit sized instructions and makes no attempt to support variable length
 // instructions. The base assembler buffer which supports variable width
 // instruction is used by the x86 and x64 backends.