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commit bd5d1fccbe09f332b8cd9a8cbbbda61fa6c48377
parent 8d47d89b0dba53b0104e5aee0baf6a890ef07706
Author: André Bargull <andre.bargull@gmail.com>
Date:   Fri, 24 Oct 2025 14:58:56 +0000

Bug 1996089: Remove unused temp register from LModI. r=spidermonkey-reviewers,jandem

And use at-start allocations for riscv64.

Differential Revision: https://phabricator.services.mozilla.com/D269846

Diffstat:
M
js/src/jit/LIROps.yaml
 | 
2
+-
M
js/src/jit/loong64/Lowering-loong64.cpp
 | 
4
++--
M
js/src/jit/mips-shared/CodeGenerator-mips-shared.cpp
 | 
5
+----
M
js/src/jit/mips-shared/Lowering-mips-shared.cpp
 | 
4
++--
M
js/src/jit/riscv64/CodeGenerator-riscv64.cpp
 | 
8
+++-----
M
js/src/jit/riscv64/Lowering-riscv64.cpp
 | 
12
++++++++++--

6 files changed, 19 insertions(+), 16 deletions(-)
diff --git a/js/src/jit/LIROps.yaml b/js/src/jit/LIROps.yaml
@@ -4090,7 +4090,7 @@
   operands:
     lhs: WordSized
     rhs: WordSized
-#if !defined(JS_CODEGEN_ARM) && !defined(JS_CODEGEN_ARM64)
+#if defined(JS_CODEGEN_X86) || defined(JS_CODEGEN_X64)
   num_temps: 1
 #endif
   mir_op: Mod
diff --git a/js/src/jit/loong64/Lowering-loong64.cpp b/js/src/jit/loong64/Lowering-loong64.cpp
@@ -242,8 +242,8 @@ void LIRGeneratorLOONG64::lowerModI(MMod* mod) {
       return;
     }
   }
-  LModI* lir = new (alloc())
-      LModI(useRegister(mod->lhs()), useRegister(mod->rhs()), temp());
+  auto* lir =
+      new (alloc()) LModI(useRegister(mod->lhs()), useRegister(mod->rhs()));
 
   if (mod->fallible()) {
     assignSnapshot(lir, mod->bailoutKind());
diff --git a/js/src/jit/mips-shared/CodeGenerator-mips-shared.cpp b/js/src/jit/mips-shared/CodeGenerator-mips-shared.cpp
@@ -595,12 +595,9 @@ void CodeGenerator::visitModI(LModI* ins) {
   Register lhs = ToRegister(ins->lhs());
   Register rhs = ToRegister(ins->rhs());
   Register dest = ToRegister(ins->output());
-  Register callTemp = ToRegister(ins->temp0());
   MMod* mir = ins->mir();
   Label done;
 
-  masm.move32(lhs, callTemp);
-
   // Prevent X % 0.
   // For X % Y, Compare Y with 0.
   // There are two cases: (Y == 0) and (Y != 0)
@@ -644,7 +641,7 @@ void CodeGenerator::visitModI(LModI* ins) {
       MOZ_ASSERT(mir->fallible());
       // See if X < 0
       masm.ma_b(dest, Imm32(0), &done, Assembler::NotEqual, ShortJump);
-      bailoutCmp32(Assembler::Signed, callTemp, Imm32(0), ins->snapshot());
+      bailoutCmp32(Assembler::Signed, lhs, Imm32(0), ins->snapshot());
     }
   }
   masm.bind(&done);
diff --git a/js/src/jit/mips-shared/Lowering-mips-shared.cpp b/js/src/jit/mips-shared/Lowering-mips-shared.cpp
@@ -218,8 +218,8 @@ void LIRGeneratorMIPSShared::lowerModI(MMod* mod) {
       return;
     }
   }
-  LModI* lir = new (alloc())
-      LModI(useRegister(mod->lhs()), useRegister(mod->rhs()), temp());
+  auto* lir =
+      new (alloc()) LModI(useRegister(mod->lhs()), useRegister(mod->rhs()));
 
   if (mod->fallible()) {
     assignSnapshot(lir, mod->bailoutKind());
diff --git a/js/src/jit/riscv64/CodeGenerator-riscv64.cpp b/js/src/jit/riscv64/CodeGenerator-riscv64.cpp
@@ -1116,16 +1116,12 @@ void CodeGenerator::visitDivPowTwoI(LDivPowTwoI* ins) {
 }
 
 void CodeGenerator::visitModI(LModI* ins) {
-  // Extract the registers from this instruction
   Register lhs = ToRegister(ins->lhs());
   Register rhs = ToRegister(ins->rhs());
   Register dest = ToRegister(ins->output());
-  Register callTemp = ToRegister(ins->temp0());
   MMod* mir = ins->mir();
   Label done;
 
-  masm.move32(lhs, callTemp);
-
   // Prevent INT_MIN % -1;
   // The integer division will give INT_MIN, but we want -(double)INT_MIN.
   if (mir->canBeNegativeDividend()) {
@@ -1174,8 +1170,10 @@ void CodeGenerator::visitModI(LModI* ins) {
   // out. -0.0|0 == 0
   if (mir->canBeNegativeDividend() && !mir->isTruncated()) {
     MOZ_ASSERT(mir->fallible());
+    MOZ_ASSERT(lhs != dest);
+
     masm.ma_b(dest, Imm32(0), &done, Assembler::NotEqual, ShortJump);
-    bailoutCmp32(Assembler::Signed, callTemp, callTemp, ins->snapshot());
+    bailoutCmp32(Assembler::Signed, lhs, lhs, ins->snapshot());
   }
   masm.bind(&done);
 }
diff --git a/js/src/jit/riscv64/Lowering-riscv64.cpp b/js/src/jit/riscv64/Lowering-riscv64.cpp
@@ -242,9 +242,17 @@ void LIRGeneratorRiscv64::lowerModI(MMod* mod) {
       return;
     }
   }
-  LModI* lir = new (alloc())
-      LModI(useRegister(mod->lhs()), useRegister(mod->rhs()), temp());
 
+  LAllocation lhs, rhs;
+  if (mod->canBeNegativeDividend() && !mod->isTruncated()) {
+    lhs = useRegister(mod->lhs());
+    rhs = useRegister(mod->rhs());
+  } else {
+    lhs = useRegisterAtStart(mod->lhs());
+    rhs = useRegisterAtStart(mod->rhs());
+  }
+
+  auto* lir = new (alloc()) LModI(lhs, rhs);
   if (mod->fallible()) {
     assignSnapshot(lir, mod->bailoutKind());
   }