tor-browser

commit baae844df37261b46795b9baaff39883a6bde9e6
parent 49a2579ade172287209d5ba5d477cbab9d1ae3ec
Author: André Bargull <andre.bargull@gmail.com>
Date:   Thu, 23 Oct 2025 12:23:35 +0000

Bug 1995707 - Part 5: Handle zero shift in arm64 codegen. r=spidermonkey-reviewers,jandem

Differential Revision: https://phabricator.services.mozilla.com/D269555

Diffstat:
M
js/src/jit-test/tests/wasm/ion-adhoc-multiplatform.js
 | 
4
++--
M
js/src/jit/arm64/CodeGenerator-arm64.cpp
 | 
44
+++++++++++++++++++++++++++-----------------

2 files changed, 29 insertions(+), 19 deletions(-)
diff --git a/js/src/jit-test/tests/wasm/ion-adhoc-multiplatform.js b/js/src/jit-test/tests/wasm/ion-adhoc-multiplatform.js
@@ -334,7 +334,7 @@ codegenTestMultiplatform_adhoc(
     {x64:   `mov %edi, %ecx
              mov %ecx, %eax`,
      x86:   `movl 0x10\\(%rbp\\), %eax`,
-     arm64: `lsr w0, w0, #0`, // lsl and lsr are both aliases for ubfm. When shift=0, the preferred disassembly of ubfm is lsr.
+     arm64: `mov w0, w0`,
      arm:   `` // no-op 
     },
     {x86: {no_prefix:true}}
@@ -387,7 +387,7 @@ codegenTestMultiplatform_adhoc(
     {x64:   `mov %edi, %ecx
              mov %ecx, %eax`,
      x86:   `movl 0x10\\(%rbp\\), %eax`,
-     arm64: `sbfx w0, w0, #0, #32`,
+     arm64: `mov w0, w0`,
      arm:   ``
     },
     {x86: {no_prefix:true}}
diff --git a/js/src/jit/arm64/CodeGenerator-arm64.cpp b/js/src/jit/arm64/CodeGenerator-arm64.cpp
@@ -882,10 +882,18 @@ void CodeGenerator::visitShiftI(LShiftI* ins) {
     int32_t shift = ToInt32(rhs) & 0x1F;
     switch (ins->bitop()) {
       case JSOp::Lsh:
-        masm.Lsl(dest, lhs, shift);
+        if (shift) {
+          masm.Lsl(dest, lhs, shift);
+        } else {
+          masm.Mov(dest, lhs);
+        }
         break;
       case JSOp::Rsh:
-        masm.Asr(dest, lhs, shift);
+        if (shift) {
+          masm.Asr(dest, lhs, shift);
+        } else {
+          masm.Mov(dest, lhs);
+        }
         break;
       case JSOp::Ursh:
         if (shift) {
@@ -931,18 +939,22 @@ void CodeGenerator::visitShiftIntPtr(LShiftIntPtr* ins) {
 
   if (rhs->isConstant()) {
     int32_t shift = ToIntPtr(rhs) & 0x3F;
-    switch (ins->bitop()) {
-      case JSOp::Lsh:
-        masm.Lsl(dest, lhs, shift);
-        break;
-      case JSOp::Rsh:
-        masm.Asr(dest, lhs, shift);
-        break;
-      case JSOp::Ursh:
-        masm.Lsr(dest, lhs, shift);
-        break;
-      default:
-        MOZ_CRASH("Unexpected shift op");
+    if (shift == 0) {
+      masm.Mov(dest, lhs);
+    } else {
+      switch (ins->bitop()) {
+        case JSOp::Lsh:
+          masm.Lsl(dest, lhs, shift);
+          break;
+        case JSOp::Rsh:
+          masm.Asr(dest, lhs, shift);
+          break;
+        case JSOp::Ursh:
+          masm.Lsr(dest, lhs, shift);
+          break;
+        default:
+          MOZ_CRASH("Unexpected shift op");
+      }
     }
   } else {
     ARMRegister rhsreg = toXRegister(rhs);
@@ -2017,9 +2029,7 @@ void CodeGenerator::visitShiftI64(LShiftI64* lir) {
   if (rhsAlloc->isConstant()) {
     int32_t shift = int32_t(rhsAlloc->toConstant()->toInt64() & 0x3F);
     if (shift == 0) {
-      if (lhs.code() != dest.code()) {
-        masm.Mov(dest, lhs);
-      }
+      masm.Mov(dest, lhs);
     } else {
       switch (lir->bitop()) {
         case JSOp::Lsh: