commit 9092fb37353a5c2ebad147352cd096bb877565c9
parent 4f8cd0f4297c2a2091ba6930d848c766b6385d31
Author: André Bargull <andre.bargull@gmail.com>
Date: Wed, 29 Oct 2025 10:22:06 +0000
Bug 1996522 - Part 1: Add xorp[sd] and andps with memory operands. r=iain
Differential Revision: https://phabricator.services.mozilla.com/D270125
Diffstat:
6 files changed, 55 insertions(+), 0 deletions(-)
diff --git a/js/src/jit/x64/BaseAssembler-x64.h b/js/src/jit/x64/BaseAssembler-x64.h
@@ -1051,9 +1051,18 @@ class BaseAssemblerX64 : public BaseAssembler {
[[nodiscard]] JmpSrc vmulpd_ripr(XMMRegisterID src, XMMRegisterID dst) {
return twoByteRipOpSimd("vmulpd", VEX_PD, OP2_MULPD_VpdWpd, src, dst);
}
+ [[nodiscard]] JmpSrc vandps_ripr(XMMRegisterID src, XMMRegisterID dst) {
+ return twoByteRipOpSimd("vandps", VEX_PS, OP2_ANDPS_VpsWps, src, dst);
+ }
[[nodiscard]] JmpSrc vandpd_ripr(XMMRegisterID src, XMMRegisterID dst) {
return twoByteRipOpSimd("vandpd", VEX_PD, OP2_ANDPD_VpdWpd, src, dst);
}
+ [[nodiscard]] JmpSrc vxorps_ripr(XMMRegisterID src, XMMRegisterID dst) {
+ return twoByteRipOpSimd("vxorps", VEX_PS, OP2_XORPS_VpsWps, src, dst);
+ }
+ [[nodiscard]] JmpSrc vxorpd_ripr(XMMRegisterID src, XMMRegisterID dst) {
+ return twoByteRipOpSimd("vxorpd", VEX_PD, OP2_XORPD_VpdWpd, src, dst);
+ }
[[nodiscard]] JmpSrc vminpd_ripr(XMMRegisterID src, XMMRegisterID dst) {
return twoByteRipOpSimd("vminpd", VEX_PD, OP2_MINPD_VpdWpd, src, dst);
}
diff --git a/js/src/jit/x64/MacroAssembler-x64.cpp b/js/src/jit/x64/MacroAssembler-x64.cpp
@@ -298,11 +298,26 @@ void MacroAssemblerX64::vmulpdSimd128(const SimdConstant& v, FloatRegister lhs,
vpRiprOpSimd128(v, lhs, dest, &X86Encoding::BaseAssemblerX64::vmulpd_ripr);
}
+void MacroAssemblerX64::vandpsSimd128(const SimdConstant& v, FloatRegister lhs,
+ FloatRegister dest) {
+ vpRiprOpSimd128(v, lhs, dest, &X86Encoding::BaseAssemblerX64::vandps_ripr);
+}
+
void MacroAssemblerX64::vandpdSimd128(const SimdConstant& v, FloatRegister lhs,
FloatRegister dest) {
vpRiprOpSimd128(v, lhs, dest, &X86Encoding::BaseAssemblerX64::vandpd_ripr);
}
+void MacroAssemblerX64::vxorpsSimd128(const SimdConstant& v, FloatRegister lhs,
+ FloatRegister dest) {
+ vpRiprOpSimd128(v, lhs, dest, &X86Encoding::BaseAssemblerX64::vxorps_ripr);
+}
+
+void MacroAssemblerX64::vxorpdSimd128(const SimdConstant& v, FloatRegister lhs,
+ FloatRegister dest) {
+ vpRiprOpSimd128(v, lhs, dest, &X86Encoding::BaseAssemblerX64::vxorpd_ripr);
+}
+
void MacroAssemblerX64::vminpdSimd128(const SimdConstant& v, FloatRegister lhs,
FloatRegister dest) {
vpRiprOpSimd128(v, lhs, dest, &X86Encoding::BaseAssemblerX64::vminpd_ripr);
diff --git a/js/src/jit/x64/MacroAssembler-x64.h b/js/src/jit/x64/MacroAssembler-x64.h
@@ -1071,8 +1071,14 @@ class MacroAssemblerX64 : public MacroAssemblerX86Shared {
FloatRegister dest);
void vmulpdSimd128(const SimdConstant& v, FloatRegister lhs,
FloatRegister dest);
+ void vandpsSimd128(const SimdConstant& v, FloatRegister lhs,
+ FloatRegister dest);
void vandpdSimd128(const SimdConstant& v, FloatRegister lhs,
FloatRegister dest);
+ void vxorpsSimd128(const SimdConstant& v, FloatRegister lhs,
+ FloatRegister dest);
+ void vxorpdSimd128(const SimdConstant& v, FloatRegister lhs,
+ FloatRegister dest);
void vminpdSimd128(const SimdConstant& v, FloatRegister lhs,
FloatRegister dest);
void vpacksswbSimd128(const SimdConstant& v, FloatRegister lhs,
diff --git a/js/src/jit/x86-shared/BaseAssembler-x86-shared.h b/js/src/jit/x86-shared/BaseAssembler-x86-shared.h
@@ -3731,6 +3731,10 @@ class BaseAssembler : public GenericAssembler {
twoByteOpSimd("vxorpd", VEX_PD, OP2_XORPD_VpdWpd, src1, src0, dst);
}
+ void vxorpd_mr(const void* address, XMMRegisterID src0, XMMRegisterID dst) {
+ twoByteOpSimd("vxorpd", VEX_PD, OP2_XORPD_VpdWpd, address, src0, dst);
+ }
+
void vorpd_rr(XMMRegisterID src1, XMMRegisterID src0, XMMRegisterID dst) {
twoByteOpSimd("vorpd", VEX_PD, OP2_ORPD_VpdWpd, src1, src0, dst);
}
diff --git a/js/src/jit/x86/MacroAssembler-x86.cpp b/js/src/jit/x86/MacroAssembler-x86.cpp
@@ -310,11 +310,26 @@ void MacroAssemblerX86::vmulpdSimd128(const SimdConstant& v, FloatRegister lhs,
vpPatchOpSimd128(v, lhs, dest, &X86Encoding::BaseAssemblerX86::vmulpd_mr);
}
+void MacroAssemblerX86::vandpsSimd128(const SimdConstant& v, FloatRegister lhs,
+ FloatRegister dest) {
+ vpPatchOpSimd128(v, lhs, dest, &X86Encoding::BaseAssemblerX86::vandps_mr);
+}
+
void MacroAssemblerX86::vandpdSimd128(const SimdConstant& v, FloatRegister lhs,
FloatRegister dest) {
vpPatchOpSimd128(v, lhs, dest, &X86Encoding::BaseAssemblerX86::vandpd_mr);
}
+void MacroAssemblerX86::vxorpsSimd128(const SimdConstant& v, FloatRegister lhs,
+ FloatRegister dest) {
+ vpPatchOpSimd128(v, lhs, dest, &X86Encoding::BaseAssemblerX86::vxorps_mr);
+}
+
+void MacroAssemblerX86::vxorpdSimd128(const SimdConstant& v, FloatRegister lhs,
+ FloatRegister dest) {
+ vpPatchOpSimd128(v, lhs, dest, &X86Encoding::BaseAssemblerX86::vxorpd_mr);
+}
+
void MacroAssemblerX86::vminpdSimd128(const SimdConstant& v, FloatRegister lhs,
FloatRegister dest) {
vpPatchOpSimd128(v, lhs, dest, &X86Encoding::BaseAssemblerX86::vminpd_mr);
diff --git a/js/src/jit/x86/MacroAssembler-x86.h b/js/src/jit/x86/MacroAssembler-x86.h
@@ -1062,8 +1062,14 @@ class MacroAssemblerX86 : public MacroAssemblerX86Shared {
FloatRegister dest);
void vmulpdSimd128(const SimdConstant& v, FloatRegister lhs,
FloatRegister dest);
+ void vandpsSimd128(const SimdConstant& v, FloatRegister lhs,
+ FloatRegister dest);
void vandpdSimd128(const SimdConstant& v, FloatRegister lhs,
FloatRegister dest);
+ void vxorpsSimd128(const SimdConstant& v, FloatRegister lhs,
+ FloatRegister dest);
+ void vxorpdSimd128(const SimdConstant& v, FloatRegister lhs,
+ FloatRegister dest);
void vminpdSimd128(const SimdConstant& v, FloatRegister lhs,
FloatRegister dest);
void vpacksswbSimd128(const SimdConstant& v, FloatRegister lhs,