tor-browser

commit 8c542131983466fa714ef0627ae83967ea3ecdbf
parent a17432cf9e6ade72d7da4f778c2083474bd190fa
Author: Xuan Chen <henry.chen@oss.cipunited.com>
Date:   Tue, 11 Nov 2025 18:04:47 +0000

Bug 1997517 - Part 5: [mips64] Improve pre-R2 compatibility of ma_liPatchable. r=anba

Instead of using drotr32, this patch uses daddiu to help UpdateLoad64Value know
if it's patching Li64 or Li48.

Differential Revision: https://phabricator.services.mozilla.com/D271760

Diffstat:
M
js/src/jit/mips-shared/MacroAssembler-mips-shared.cpp
 | 
2
+-
M
js/src/jit/mips64/Assembler-mips64.cpp
 | 
20
++++++++++----------
M
js/src/jit/mips64/MacroAssembler-mips64.cpp
 | 
6
+++---

3 files changed, 14 insertions(+), 14 deletions(-)
diff --git a/js/src/jit/mips-shared/MacroAssembler-mips-shared.cpp b/js/src/jit/mips-shared/MacroAssembler-mips-shared.cpp
@@ -1870,7 +1870,7 @@ void MacroAssembler::call(JitCode* c) {
 CodeOffset MacroAssembler::nopPatchableToCall() {
   as_nop();  // lui
   as_nop();  // ori
-  as_nop();  // drotr32
+  as_nop();  // dsll
   as_nop();  // ori
   as_nop();  // jalr
   as_nop();
diff --git a/js/src/jit/mips64/Assembler-mips64.cpp b/js/src/jit/mips64/Assembler-mips64.cpp
@@ -268,11 +268,11 @@ uint64_t Assembler::ExtractLoad64Value(Instruction* inst0) {
   InstImm* i5 = (InstImm*)i3->next()->next();
 
   MOZ_ASSERT(i0->extractOpcode() == ((uint32_t)op_lui >> OpcodeShift));
-  MOZ_ASSERT(i1->extractOpcode() == ((uint32_t)op_ori >> OpcodeShift));
+  MOZ_ASSERT(i1->extractOpcode() == ((uint32_t)op_ori >> OpcodeShift) ||
+             i1->extractOpcode() == ((uint32_t)op_daddiu >> OpcodeShift));
   MOZ_ASSERT(i3->extractOpcode() == ((uint32_t)op_ori >> OpcodeShift));
 
-  if ((i2->extractOpcode() == ((uint32_t)op_special >> OpcodeShift)) &&
-      (i2->extractFunctionField() == ff_dsrl32)) {
+  if (i1->extractOpcode() == ((uint32_t)op_ori >> OpcodeShift)) {
     uint64_t value = (uint64_t(i0->extractImm16Value()) << 32) |
                      (uint64_t(i1->extractImm16Value()) << 16) |
                      uint64_t(i3->extractImm16Value());
@@ -280,8 +280,8 @@ uint64_t Assembler::ExtractLoad64Value(Instruction* inst0) {
   }
 
   MOZ_ASSERT(i5->extractOpcode() == ((uint32_t)op_ori >> OpcodeShift));
-  uint64_t value = (uint64_t(i0->extractImm16Value()) << 48) |
-                   (uint64_t(i1->extractImm16Value()) << 32) |
+  uint64_t value = ((uint64_t(i0->extractImm16Value()) << 48) +
+                    ((int64_t(i1->extractImm16Value()) << 48) >> 16)) |
                    (uint64_t(i3->extractImm16Value()) << 16) |
                    uint64_t(i5->extractImm16Value());
   return value;
@@ -295,11 +295,11 @@ void Assembler::UpdateLoad64Value(Instruction* inst0, uint64_t value) {
   InstImm* i5 = (InstImm*)i3->next()->next();
 
   MOZ_ASSERT(i0->extractOpcode() == ((uint32_t)op_lui >> OpcodeShift));
-  MOZ_ASSERT(i1->extractOpcode() == ((uint32_t)op_ori >> OpcodeShift));
+  MOZ_ASSERT(i1->extractOpcode() == ((uint32_t)op_ori >> OpcodeShift) ||
+             i1->extractOpcode() == ((uint32_t)op_daddiu >> OpcodeShift));
   MOZ_ASSERT(i3->extractOpcode() == ((uint32_t)op_ori >> OpcodeShift));
 
-  if ((i2->extractOpcode() == ((uint32_t)op_special >> OpcodeShift)) &&
-      (i2->extractFunctionField() == ff_dsrl32)) {
+  if (i1->extractOpcode() == ((uint32_t)op_ori >> OpcodeShift)) {
     i0->setImm16(Imm16::Lower(Imm32(value >> 32)));
     i1->setImm16(Imm16::Upper(Imm32(value)));
     i3->setImm16(Imm16::Lower(Imm32(value)));
@@ -308,7 +308,7 @@ void Assembler::UpdateLoad64Value(Instruction* inst0, uint64_t value) {
 
   MOZ_ASSERT(i5->extractOpcode() == ((uint32_t)op_ori >> OpcodeShift));
 
-  i0->setImm16(Imm16::Upper(Imm32(value >> 32)));
+  i0->setImm16(Imm16::Upper(Imm32((value >> 32) + 0x8000)));
   i1->setImm16(Imm16::Lower(Imm32(value >> 32)));
   i3->setImm16(Imm16::Upper(Imm32(value)));
   i5->setImm16(Imm16::Lower(Imm32(value)));
@@ -322,7 +322,7 @@ void Assembler::WriteLoad64Instructions(Instruction* inst0, Register reg,
 
   *inst0 = InstImm(op_lui, zero, reg, Imm16::Lower(Imm32(value >> 32)));
   *inst1 = InstImm(op_ori, reg, reg, Imm16::Upper(Imm32(value)));
-  *inst2 = InstReg(op_special, rs_one, reg, reg, 48 - 32, ff_dsrl32);
+  *inst2 = InstReg(op_special, rs_zero, reg, reg, 16, ff_dsll);
   *inst3 = InstImm(op_ori, reg, reg, Imm16::Lower(Imm32(value)));
 }
 
diff --git a/js/src/jit/mips64/MacroAssembler-mips64.cpp b/js/src/jit/mips64/MacroAssembler-mips64.cpp
@@ -273,8 +273,8 @@ void MacroAssemblerMIPS64::ma_liPatchable(Register dest, ImmWord imm,
                                           LiFlags flags) {
   if (Li64 == flags) {
     m_buffer.ensureSpace(6 * sizeof(uint32_t));
-    as_lui(dest, Imm16::Upper(Imm32(imm.value >> 32)).encode());
-    as_ori(dest, dest, Imm16::Lower(Imm32(imm.value >> 32)).encode());
+    as_lui(dest, Imm16::Upper(Imm32((imm.value >> 32) + 0x8000)).encode());
+    as_daddiu(dest, dest, int16_t((imm.value >> 32) & 0xffff));
     as_dsll(dest, dest, 16);
     as_ori(dest, dest, Imm16::Upper(Imm32(imm.value)).encode());
     as_dsll(dest, dest, 16);
@@ -283,7 +283,7 @@ void MacroAssemblerMIPS64::ma_liPatchable(Register dest, ImmWord imm,
     m_buffer.ensureSpace(4 * sizeof(uint32_t));
     as_lui(dest, Imm16::Lower(Imm32(imm.value >> 32)).encode());
     as_ori(dest, dest, Imm16::Upper(Imm32(imm.value)).encode());
-    as_drotr32(dest, dest, 48);
+    as_dsll(dest, dest, 16);
     as_ori(dest, dest, Imm16::Lower(Imm32(imm.value)).encode());
   }
 }