commit 8baee45cfa696352933ddd3e7cd9dcd07071bbe1
parent 776588aa7902ed4bac9831a6127163f24bc13b5b
Author: Xuan Chen <henry.chen@oss.cipunited.com>
Date: Tue, 11 Nov 2025 18:04:46 +0000
Bug 1997517 - Part 2: [mips64] Remove mips32-only assertions. r=anba
Floating-point conversions targeting 64-bit integers are missing in pre-R2
MIPS32 hardware, but they always exist in MIPS64.
Differential Revision: https://phabricator.services.mozilla.com/D271757
Diffstat:
1 file changed, 0 insertions(+), 4 deletions(-)
diff --git a/js/src/jit/mips-shared/Assembler-mips-shared.cpp b/js/src/jit/mips-shared/Assembler-mips-shared.cpp
@@ -1394,7 +1394,6 @@ BufferOffset AssemblerMIPSShared::as_truncws(FloatRegister fd,
BufferOffset AssemblerMIPSShared::as_truncls(FloatRegister fd,
FloatRegister fs) {
spew("trunc.l.s%3s,%3s", fd.name(), fs.name());
- MOZ_ASSERT(hasR2());
return writeInst(
InstReg(op_cop1, rs_s, zero, fs, fd, ff_trunc_l_fmt).encode());
}
@@ -1451,14 +1450,12 @@ BufferOffset AssemblerMIPSShared::as_truncwd(FloatRegister fd,
BufferOffset AssemblerMIPSShared::as_truncld(FloatRegister fd,
FloatRegister fs) {
spew("trunc.l.d%3s,%3s", fd.name(), fs.name());
- MOZ_ASSERT(hasR2());
return writeInst(
InstReg(op_cop1, rs_d, zero, fs, fd, ff_trunc_l_fmt).encode());
}
BufferOffset AssemblerMIPSShared::as_cvtdl(FloatRegister fd, FloatRegister fs) {
spew("cvt.d.l%3s,%3s", fd.name(), fs.name());
- MOZ_ASSERT(hasR2());
return writeInst(InstReg(op_cop1, rs_l, zero, fs, fd, ff_cvt_d_fmt).encode());
}
@@ -1479,7 +1476,6 @@ BufferOffset AssemblerMIPSShared::as_cvtsd(FloatRegister fd, FloatRegister fs) {
BufferOffset AssemblerMIPSShared::as_cvtsl(FloatRegister fd, FloatRegister fs) {
spew("cvt.s.l%3s,%3s", fd.name(), fs.name());
- MOZ_ASSERT(hasR2());
return writeInst(InstReg(op_cop1, rs_l, zero, fs, fd, ff_cvt_s_fmt).encode());
}