commit 81a2dd4de1abc2b3fdfb87a2bb509cd7e32142ed
parent 34de8212a70815d504d03d80ef1b411e0bb9f881
Author: André Bargull <andre.bargull@gmail.com>
Date: Mon, 10 Nov 2025 15:13:42 +0000
Bug 1998457 - Part 2: Add imulq and umulq. r=spidermonkey-reviewers,iain
Add `imulq` and `umulq` similar to `imull` and `umull`.
Used in the next part.
Differential Revision: https://phabricator.services.mozilla.com/D271437
Diffstat:
2 files changed, 16 insertions(+), 0 deletions(-)
diff --git a/js/src/jit/x64/Assembler-x64.h b/js/src/jit/x64/Assembler-x64.h
@@ -962,6 +962,12 @@ class Assembler : public AssemblerX86Shared {
masm.popcntq_rr(src.encoding(), dest.encoding());
}
+ void imulq(Register multiplier) {
+ // Consumes rax as the other argument and clobbers rdx, as the result is in
+ // rdx:rax.
+ masm.imulq_r(multiplier.encoding());
+ }
+ void umulq(Register multiplier) { masm.mulq_r(multiplier.encoding()); }
void imulq(Imm32 imm, Register src, Register dest) {
masm.imulq_ir(imm.value, src.encoding(), dest.encoding());
}
diff --git a/js/src/jit/x64/BaseAssembler-x64.h b/js/src/jit/x64/BaseAssembler-x64.h
@@ -408,6 +408,11 @@ class BaseAssemblerX64 : public BaseAssembler {
m_formatter.twoByteOp64(OP2_IMUL_GvEv, src, dst);
}
+ void imulq_r(RegisterID multiplier) {
+ spew("imulq %s", GPReg64Name(multiplier));
+ m_formatter.oneByteOp64(OP_GROUP3_Ev, multiplier, GROUP3_OP_IMUL);
+ }
+
void imulq_mr(int32_t offset, RegisterID base, RegisterID dst) {
spew("imulq " MEM_ob ", %s", ADDR_ob(offset, base), GPReg64Name(dst));
m_formatter.twoByteOp64(OP2_IMUL_GvEv, offset, base, dst);
@@ -424,6 +429,11 @@ class BaseAssemblerX64 : public BaseAssembler {
}
}
+ void mulq_r(RegisterID multiplier) {
+ spew("mulq %s", GPReg64Name(multiplier));
+ m_formatter.oneByteOp64(OP_GROUP3_Ev, multiplier, GROUP3_OP_MUL);
+ }
+
void cqo() {
spew("cqo ");
m_formatter.oneByteOp64(OP_CDQ);