tor-browser

commit 3951789f40b800fcda77edb7eed51adeffcf2406
parent 3c5ab0e82dccef9f3ccb8f726ab514ce5181c4a6
Author: André Bargull <andre.bargull@gmail.com>
Date:   Thu, 23 Oct 2025 12:23:35 +0000

Bug 1995707 - Part 2: Use at-start for shift and rotate instructions on arm32 and arm64. r=spidermonkey-reviewers,jandem

Delegating to `lowerForALU` changes the allocation to use at-start.

Differential Revision: https://phabricator.services.mozilla.com/D269552

Diffstat:
M
js/src/jit-test/tests/wasm/ion-adhoc-multiplatform.js
 | 
25
++++++-------------------
M
js/src/jit/arm/CodeGenerator-arm.cpp
 | 
9
+++++----
M
js/src/jit/arm/Lowering-arm.cpp
 | 
4
+---
M
js/src/jit/arm64/Lowering-arm64.cpp
 | 
4
+---

4 files changed, 13 insertions(+), 29 deletions(-)
diff --git a/js/src/jit-test/tests/wasm/ion-adhoc-multiplatform.js b/js/src/jit-test/tests/wasm/ion-adhoc-multiplatform.js
@@ -335,13 +335,8 @@ codegenTestMultiplatform_adhoc(
     {x64:   `mov %edi, %ecx
              mov %ecx, %eax`,
      x86:   `movl 0x10\\(%rbp\\), %eax`,
-     arm64: // Regalloc badness, plus not folded out at the MIR level
-            `mov w2, w0
-             mov w1, w2
-             lsr w0, w1, #0`, // Uhh.  lsr ?!
-     arm:   `mov r2, r0
-             mov r1, r2
-             mov r0, r1`
+     arm64: `lsr w0, w0, #0`, // lsl and lsr are both aliases for ubfm. When shift=0, the preferred disassembly of ubfm is lsr.
+     arm:   `` // no-op 
     },
     {x86: {no_prefix:true}}
 );
@@ -367,12 +362,8 @@ codegenTestMultiplatform_adhoc(
     {x64:   `mov %edi, %ecx
              mov %ecx, %eax`,
      x86:   `movl 0x10\\(%rbp\\), %eax`,
-     arm64: `mov w2, w0
-             mov w1, w2
-             mov w0, w1`,
-     arm:   `mov r2, r0
-             mov r1, r2
-             mov r0, r1`
+     arm64: `mov w0, w0`,
+     arm:   ``
     },
     {x86: {no_prefix:true}}
 );
@@ -397,12 +388,8 @@ codegenTestMultiplatform_adhoc(
     {x64:   `mov %edi, %ecx
              mov %ecx, %eax`,
      x86:   `movl 0x10\\(%rbp\\), %eax`,
-     arm64: `mov w2, w0
-             mov w1, w2
-             sbfx w0, w1, #0, #32`,
-     arm:   `mov r2, r0
-             mov r1, r2
-             mov r0, r1`
+     arm64: `sbfx w0, w0, #0, #32`,
+     arm:   ``
     },
     {x86: {no_prefix:true}}
 );
diff --git a/js/src/jit/arm/CodeGenerator-arm.cpp b/js/src/jit/arm/CodeGenerator-arm.cpp
@@ -994,17 +994,18 @@ void CodeGenerator::visitShiftI(LShiftI* ins) {
     // The shift amounts should be AND'ed into the 0-31 range since arm
     // shifts by the lower byte of the register (it will attempt to shift by
     // 250 if you ask it to).
-    masm.as_and(dest, ToRegister(rhs), Imm8(0x1F));
+    ScratchRegisterScope scratch(masm);
+    masm.as_and(scratch, ToRegister(rhs), Imm8(0x1F));
 
     switch (ins->bitop()) {
       case JSOp::Lsh:
-        masm.ma_lsl(dest, lhs, dest);
+        masm.ma_lsl(scratch, lhs, dest);
         break;
       case JSOp::Rsh:
-        masm.ma_asr(dest, lhs, dest);
+        masm.ma_asr(scratch, lhs, dest);
         break;
       case JSOp::Ursh:
-        masm.ma_lsr(dest, lhs, dest);
+        masm.ma_lsr(scratch, lhs, dest);
         if (ins->mir()->toUrsh()->fallible()) {
           // x >>> 0 can overflow.
           masm.as_cmp(dest, Imm8(0));
diff --git a/js/src/jit/arm/Lowering-arm.cpp b/js/src/jit/arm/Lowering-arm.cpp
@@ -267,9 +267,7 @@ void LIRGeneratorARM::lowerUntypedPhiInput(MPhi* phi, uint32_t inputPosition,
 void LIRGeneratorARM::lowerForShift(LInstructionHelper<1, 2, 0>* ins,
                                     MDefinition* mir, MDefinition* lhs,
                                     MDefinition* rhs) {
-  ins->setOperand(0, useRegister(lhs));
-  ins->setOperand(1, useRegisterOrConstant(rhs));
-  define(ins, mir);
+  lowerForALU(ins, mir, lhs, rhs);
 }
 
 template <class LInstr>
diff --git a/js/src/jit/arm64/Lowering-arm64.cpp b/js/src/jit/arm64/Lowering-arm64.cpp
@@ -209,9 +209,7 @@ void LIRGeneratorARM64::lowerUntypedPhiInput(MPhi* phi, uint32_t inputPosition,
 void LIRGeneratorARM64::lowerForShift(LInstructionHelper<1, 2, 0>* ins,
                                       MDefinition* mir, MDefinition* lhs,
                                       MDefinition* rhs) {
-  ins->setOperand(0, useRegister(lhs));
-  ins->setOperand(1, useRegisterOrConstant(rhs));
-  define(ins, mir);
+  lowerForALU(ins, mir, lhs, rhs);
 }
 
 void LIRGeneratorARM64::lowerDivI(MDiv* div) {