itx.h (4977B)
1 /* 2 * Copyright © 2023, VideoLAN and dav1d authors 3 * Copyright © 2023, Loongson Technology Corporation Limited 4 * All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions are met: 8 * 9 * 1. Redistributions of source code must retain the above copyright notice, this 10 * list of conditions and the following disclaimer. 11 * 12 * 2. Redistributions in binary form must reproduce the above copyright notice, 13 * this list of conditions and the following disclaimer in the documentation 14 * and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND 17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 18 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 19 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR 20 * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 21 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 22 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND 23 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 24 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS 25 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 26 */ 27 28 #ifndef DAV1D_SRC_LOONGARCH_ITX_H 29 #define DAV1D_SRC_LOONGARCH_ITX_H 30 31 #include "src/cpu.h" 32 #include "src/itx.h" 33 34 decl_itx17_fns( 4, 4, lsx); 35 decl_itx16_fns( 4, 8, lsx); 36 decl_itx16_fns( 4, 16, lsx); 37 decl_itx16_fns( 8, 4, lsx); 38 decl_itx16_fns( 8, 8, lsx); 39 decl_itx16_fns( 8, 16, lsx); 40 decl_itx2_fns ( 8, 32, lsx); 41 decl_itx16_fns(16, 8, lsx); 42 43 decl_itx_fn(BF(dav1d_inv_txfm_add_dct_dct_16x4, lsx)); 44 decl_itx_fn(BF(dav1d_inv_txfm_add_identity_identity_16x4, lsx)); 45 decl_itx_fn(BF(dav1d_inv_txfm_add_adst_dct_16x4, lsx)); 46 47 decl_itx_fn(BF(dav1d_inv_txfm_add_dct_dct_16x16, lsx)); 48 decl_itx_fn(BF(dav1d_inv_txfm_add_adst_adst_16x16, lsx)); 49 decl_itx_fn(BF(dav1d_inv_txfm_add_adst_dct_16x16, lsx)); 50 decl_itx_fn(BF(dav1d_inv_txfm_add_dct_adst_16x16, lsx)); 51 decl_itx_fn(BF(dav1d_inv_txfm_add_flipadst_dct_16x16, lsx)); 52 decl_itx_fn(BF(dav1d_inv_txfm_add_dct_flipadst_16x16, lsx)); 53 decl_itx_fn(BF(dav1d_inv_txfm_add_adst_flipadst_16x16, lsx)); 54 decl_itx_fn(BF(dav1d_inv_txfm_add_flipadst_adst_16x16, lsx)); 55 56 decl_itx_fn(BF(dav1d_inv_txfm_add_dct_dct_16x32, lsx)); 57 58 decl_itx_fn(BF(dav1d_inv_txfm_add_dct_dct_32x8, lsx)); 59 60 decl_itx_fn(BF(dav1d_inv_txfm_add_dct_dct_32x16, lsx)); 61 62 decl_itx_fn(BF(dav1d_inv_txfm_add_dct_dct_32x32, lsx)); 63 64 decl_itx_fn(BF(dav1d_inv_txfm_add_dct_dct_64x32, lsx)); 65 66 decl_itx_fn(BF(dav1d_inv_txfm_add_dct_dct_64x64, lsx)); 67 68 decl_itx_fn(BF(dav1d_inv_txfm_add_adst_adst_16x16, lasx)); 69 70 static ALWAYS_INLINE void itx_dsp_init_loongarch(Dav1dInvTxfmDSPContext *const c, int bpc) { 71 #if BITDEPTH == 8 72 const unsigned flags = dav1d_get_cpu_flags(); 73 74 if (!(flags & DAV1D_LOONGARCH_CPU_FLAG_LSX)) return; 75 76 if (BITDEPTH != 8 ) return; 77 78 assign_itx17_fn( , 4, 4, lsx); 79 assign_itx16_fn(R, 4, 8, lsx); 80 assign_itx16_fn(R, 4, 16, lsx); 81 assign_itx16_fn(R, 8, 4, lsx); 82 assign_itx16_fn( , 8, 8, lsx); 83 assign_itx16_fn(R, 8, 16, lsx); 84 assign_itx2_fn (R, 8, 32, lsx); 85 assign_itx16_fn(R, 16, 8, lsx); 86 assign_itx1_fn (R, 64, 32, lsx); 87 assign_itx1_fn ( , 64, 64, lsx); 88 89 c->itxfm_add[RTX_16X4][DCT_DCT] = dav1d_inv_txfm_add_dct_dct_16x4_8bpc_lsx; 90 c->itxfm_add[RTX_16X4][IDTX] = dav1d_inv_txfm_add_identity_identity_16x4_8bpc_lsx; 91 c->itxfm_add[RTX_16X4][DCT_ADST] = dav1d_inv_txfm_add_adst_dct_16x4_8bpc_lsx; 92 93 c->itxfm_add[TX_16X16][DCT_DCT] = dav1d_inv_txfm_add_dct_dct_16x16_8bpc_lsx; 94 c->itxfm_add[TX_16X16][ADST_ADST] = dav1d_inv_txfm_add_adst_adst_16x16_8bpc_lsx; 95 c->itxfm_add[TX_16X16][DCT_ADST] = dav1d_inv_txfm_add_adst_dct_16x16_8bpc_lsx; 96 c->itxfm_add[TX_16X16][ADST_DCT] = dav1d_inv_txfm_add_dct_adst_16x16_8bpc_lsx; 97 c->itxfm_add[TX_16X16][DCT_FLIPADST] = dav1d_inv_txfm_add_flipadst_dct_16x16_8bpc_lsx; 98 c->itxfm_add[TX_16X16][FLIPADST_DCT] = dav1d_inv_txfm_add_dct_flipadst_16x16_8bpc_lsx; 99 c->itxfm_add[TX_16X16][FLIPADST_ADST] = dav1d_inv_txfm_add_adst_flipadst_16x16_8bpc_lsx; 100 c->itxfm_add[TX_16X16][ADST_FLIPADST] = dav1d_inv_txfm_add_flipadst_adst_16x16_8bpc_lsx; 101 102 c->itxfm_add[RTX_16X32][DCT_DCT] = dav1d_inv_txfm_add_dct_dct_16x32_8bpc_lsx; 103 104 c->itxfm_add[RTX_32X8][DCT_DCT] = dav1d_inv_txfm_add_dct_dct_32x8_8bpc_lsx; 105 106 c->itxfm_add[RTX_32X16][DCT_DCT] = dav1d_inv_txfm_add_dct_dct_32x16_8bpc_lsx; 107 108 c->itxfm_add[TX_32X32][DCT_DCT] = dav1d_inv_txfm_add_dct_dct_32x32_8bpc_lsx; 109 110 if (!(flags & DAV1D_LOONGARCH_CPU_FLAG_LASX)) return; 111 112 if (BITDEPTH != 8 ) return; 113 114 c->itxfm_add[TX_16X16][ADST_ADST] = dav1d_inv_txfm_add_adst_adst_16x16_8bpc_lasx; 115 116 #endif 117 } 118 119 #endif /* DAV1D_SRC_LOONGARCH_ITX_H */