randen_detect.cc (9592B)
1 // Copyright 2017 The Abseil Authors. 2 // 3 // Licensed under the Apache License, Version 2.0 (the "License"); 4 // you may not use this file except in compliance with the License. 5 // You may obtain a copy of the License at 6 // 7 // https://www.apache.org/licenses/LICENSE-2.0 8 // 9 // Unless required by applicable law or agreed to in writing, software 10 // distributed under the License is distributed on an "AS IS" BASIS, 11 // WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 12 // See the License for the specific language governing permissions and 13 // limitations under the License. 14 15 // HERMETIC NOTE: The randen_hwaes target must not introduce duplicate 16 // symbols from arbitrary system and other headers, since it may be built 17 // with different flags from other targets, using different levels of 18 // optimization, potentially introducing ODR violations. 19 20 #include "absl/random/internal/randen_detect.h" 21 22 #if defined(__APPLE__) && defined(__aarch64__) 23 #if defined(__has_include) 24 #if __has_include(<arm/cpu_capabilities_public.h>) 25 #include <arm/cpu_capabilities_public.h> 26 #endif 27 #endif 28 #include <sys/sysctl.h> 29 #include <sys/types.h> 30 #endif 31 32 #include <cstdint> 33 #include <cstring> 34 35 #include "absl/random/internal/platform.h" 36 #include "absl/types/optional.h" // IWYU pragma: keep 37 38 #if !defined(__UCLIBC__) && defined(__GLIBC__) && \ 39 (__GLIBC__ > 2 || (__GLIBC__ == 2 && __GLIBC_MINOR__ >= 16)) 40 #define ABSL_HAVE_GETAUXVAL 41 #endif 42 43 #if defined(ABSL_ARCH_X86_64) 44 #define ABSL_INTERNAL_USE_X86_CPUID 45 #elif defined(ABSL_ARCH_PPC) || defined(ABSL_ARCH_ARM) || \ 46 defined(ABSL_ARCH_AARCH64) 47 #if defined(__ANDROID__) 48 #define ABSL_INTERNAL_USE_ANDROID_GETAUXVAL 49 #define ABSL_INTERNAL_USE_GETAUXVAL 50 #elif defined(__linux__) && defined(ABSL_HAVE_GETAUXVAL) 51 #define ABSL_INTERNAL_USE_LINUX_GETAUXVAL 52 #define ABSL_INTERNAL_USE_GETAUXVAL 53 #endif 54 #endif 55 56 #if defined(ABSL_INTERNAL_USE_X86_CPUID) 57 #if defined(_WIN32) || defined(_WIN64) 58 #include <intrin.h> // NOLINT(build/include_order) 59 #elif ABSL_HAVE_BUILTIN(__cpuid) 60 // MSVC-equivalent __cpuid intrinsic declaration for clang-like compilers 61 // for non-Windows build environments. 62 extern void __cpuid(int[4], int); 63 #else 64 // MSVC-equivalent __cpuid intrinsic function. 65 static void __cpuid(int cpu_info[4], int info_type) { 66 __asm__ volatile("cpuid \n\t" 67 : "=a"(cpu_info[0]), "=b"(cpu_info[1]), "=c"(cpu_info[2]), 68 "=d"(cpu_info[3]) 69 : "a"(info_type), "c"(0)); 70 } 71 #endif 72 #endif // ABSL_INTERNAL_USE_X86_CPUID 73 74 // On linux, just use the c-library getauxval call. 75 #if defined(ABSL_INTERNAL_USE_LINUX_GETAUXVAL) 76 77 #include <sys/auxv.h> 78 79 static uint32_t GetAuxval(uint32_t hwcap_type) { 80 return static_cast<uint32_t>(getauxval(hwcap_type)); 81 } 82 83 #endif 84 85 // On android, probe the system's C library for getauxval(). 86 // This is the same technique used by the android NDK cpu features library 87 // as well as the google open-source cpu_features library. 88 // 89 // TODO(absl-team): Consider implementing a fallback of directly reading 90 // /proc/self/auxval. 91 #if defined(ABSL_INTERNAL_USE_ANDROID_GETAUXVAL) 92 #include <dlfcn.h> 93 94 static uint32_t GetAuxval(uint32_t hwcap_type) { 95 // NOLINTNEXTLINE(runtime/int) 96 typedef unsigned long (*getauxval_func_t)(unsigned long); 97 98 dlerror(); // Cleaning error state before calling dlopen. 99 void* libc_handle = dlopen("libc.so", RTLD_NOW); 100 if (!libc_handle) { 101 return 0; 102 } 103 uint32_t result = 0; 104 void* sym = dlsym(libc_handle, "getauxval"); 105 if (sym) { 106 getauxval_func_t func; 107 memcpy(&func, &sym, sizeof(func)); 108 result = static_cast<uint32_t>((*func)(hwcap_type)); 109 } 110 dlclose(libc_handle); 111 return result; 112 } 113 114 #endif 115 116 #if defined(__APPLE__) && defined(ABSL_ARCH_AARCH64) 117 template <typename T> 118 static absl::optional<T> ReadSysctlByName(const char* name) { 119 T val; 120 size_t val_size = sizeof(T); 121 int ret = sysctlbyname(name, &val, &val_size, nullptr, 0); 122 if (ret == -1) { 123 return absl::nullopt; 124 } 125 return val; 126 } 127 #endif 128 129 namespace absl { 130 ABSL_NAMESPACE_BEGIN 131 namespace random_internal { 132 133 // The default return at the end of the function might be unreachable depending 134 // on the configuration. Ignore that warning. 135 #if defined(__clang__) 136 #pragma clang diagnostic push 137 #pragma clang diagnostic ignored "-Wunreachable-code-return" 138 #endif 139 140 // CPUSupportsRandenHwAes returns whether the CPU is a microarchitecture 141 // which supports the crpyto/aes instructions or extensions necessary to use the 142 // accelerated RandenHwAes implementation. 143 // 144 // 1. For x86 it is sufficient to use the CPUID instruction to detect whether 145 // the cpu supports AES instructions. Done. 146 // 147 // Fon non-x86 it is much more complicated. 148 // 149 // 2. When ABSL_INTERNAL_USE_GETAUXVAL is defined, use getauxval() (either 150 // the direct c-library version, or the android probing version which loads 151 // libc), and read the hardware capability bits. 152 // This is based on the technique used by boringssl uses to detect 153 // cpu capabilities, and should allow us to enable crypto in the android 154 // builds where it is supported. 155 // 156 // 3. When __APPLE__ is defined on AARCH64, use sysctlbyname(). 157 // 158 // 4. Use the default for the compiler architecture. 159 // 160 161 bool CPUSupportsRandenHwAes() { 162 #if defined(ABSL_INTERNAL_USE_X86_CPUID) 163 // 1. For x86: Use CPUID to detect the required AES instruction set. 164 int regs[4]; 165 __cpuid(reinterpret_cast<int*>(regs), 1); 166 return regs[2] & (1 << 25); // AES 167 168 #elif defined(ABSL_INTERNAL_USE_GETAUXVAL) 169 // 2. Use getauxval() to read the hardware bits and determine 170 // cpu capabilities. 171 172 #define AT_HWCAP 16 173 #define AT_HWCAP2 26 174 #if defined(ABSL_ARCH_PPC) 175 // For Power / PPC: Expect that the cpu supports VCRYPTO 176 // See https://members.openpowerfoundation.org/document/dl/576 177 // VCRYPTO should be present in POWER8 >= 2.07. 178 // Uses Linux kernel constants from arch/powerpc/include/uapi/asm/cputable.h 179 static const uint32_t kVCRYPTO = 0x02000000; 180 const uint32_t hwcap = GetAuxval(AT_HWCAP2); 181 return (hwcap & kVCRYPTO) != 0; 182 183 #elif defined(ABSL_ARCH_ARM) 184 // For ARM: Require crypto+neon 185 // http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.ddi0500f/CIHBIBBA.html 186 // Uses Linux kernel constants from arch/arm64/include/asm/hwcap.h 187 static const uint32_t kNEON = 1 << 12; 188 uint32_t hwcap = GetAuxval(AT_HWCAP); 189 if ((hwcap & kNEON) == 0) { 190 return false; 191 } 192 193 // And use it again to detect AES. 194 static const uint32_t kAES = 1 << 0; 195 const uint32_t hwcap2 = GetAuxval(AT_HWCAP2); 196 return (hwcap2 & kAES) != 0; 197 198 #elif defined(ABSL_ARCH_AARCH64) 199 // For AARCH64: Require crypto+neon 200 // http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.ddi0500f/CIHBIBBA.html 201 static const uint32_t kNEON = 1 << 1; 202 static const uint32_t kAES = 1 << 3; 203 const uint32_t hwcap = GetAuxval(AT_HWCAP); 204 return ((hwcap & kNEON) != 0) && ((hwcap & kAES) != 0); 205 #endif 206 207 #elif defined(__APPLE__) && defined(ABSL_ARCH_AARCH64) 208 // 3. Use sysctlbyname. 209 210 // Newer XNU kernels support querying all capabilities in a single 211 // sysctlbyname. 212 #if defined(CAP_BIT_AdvSIMD) && defined(CAP_BIT_FEAT_AES) 213 static const absl::optional<uint64_t> caps = 214 ReadSysctlByName<uint64_t>("hw.optional.arm.caps"); 215 if (caps.has_value()) { 216 constexpr uint64_t kNeonAndAesCaps = 217 (uint64_t{1} << CAP_BIT_AdvSIMD) | (uint64_t{1} << CAP_BIT_FEAT_AES); 218 return (*caps & kNeonAndAesCaps) == kNeonAndAesCaps; 219 } 220 #endif 221 222 // https://developer.apple.com/documentation/kernel/1387446-sysctlbyname/determining_instruction_set_characteristics#overview 223 static const absl::optional<int> adv_simd = 224 ReadSysctlByName<int>("hw.optional.AdvSIMD"); 225 if (adv_simd.value_or(0) == 0) { 226 return false; 227 } 228 // https://developer.apple.com/documentation/kernel/1387446-sysctlbyname/determining_instruction_set_characteristics#3918855 229 static const absl::optional<int> feat_aes = 230 ReadSysctlByName<int>("hw.optional.arm.FEAT_AES"); 231 if (feat_aes.value_or(0) == 0) { 232 return false; 233 } 234 return true; 235 #else // ABSL_INTERNAL_USE_GETAUXVAL 236 // 4. By default, assume that the compiler default. 237 return ABSL_HAVE_ACCELERATED_AES ? true : false; 238 239 #endif 240 // NOTE: There are some other techniques that may be worth trying: 241 // 242 // * Use an environment variable: ABSL_RANDOM_USE_HWAES 243 // 244 // * Rely on compiler-generated target-based dispatch. 245 // Using x86/gcc it might look something like this: 246 // 247 // int __attribute__((target("aes"))) HasAes() { return 1; } 248 // int __attribute__((target("default"))) HasAes() { return 0; } 249 // 250 // This does not work on all architecture/compiler combinations. 251 // 252 // * On Linux consider reading /proc/cpuinfo and/or /proc/self/auxv. 253 // These files have lines which are easy to parse; for ARM/AARCH64 it is quite 254 // easy to find the Features: line and extract aes / neon. Likewise for 255 // PPC. 256 // 257 // * Fork a process and test for SIGILL: 258 // 259 // * Many architectures have instructions to read the ISA. Unfortunately 260 // most of those require that the code is running in ring 0 / 261 // protected-mode. 262 // 263 // There are several examples. e.g. Valgrind detects PPC ISA 2.07: 264 // https://github.com/lu-zero/valgrind/blob/master/none/tests/ppc64/test_isa_2_07_part1.c 265 // 266 // MRS <Xt>, ID_AA64ISAR0_EL1 ; Read ID_AA64ISAR0_EL1 into Xt 267 // 268 // uint64_t val; 269 // __asm __volatile("mrs %0, id_aa64isar0_el1" :"=&r" (val)); 270 // 271 // * Use a CPUID-style heuristic database. 272 } 273 274 #if defined(__clang__) 275 #pragma clang diagnostic pop 276 #endif 277 278 } // namespace random_internal 279 ABSL_NAMESPACE_END 280 } // namespace absl