jchuff-neon.c (18356B)
1 /* 2 * jchuff-neon.c - Huffman entropy encoding (64-bit Arm Neon) 3 * 4 * Copyright (C) 2020-2021, Arm Limited. All Rights Reserved. 5 * Copyright (C) 2020, 2022, D. R. Commander. All Rights Reserved. 6 * 7 * This software is provided 'as-is', without any express or implied 8 * warranty. In no event will the authors be held liable for any damages 9 * arising from the use of this software. 10 * 11 * Permission is granted to anyone to use this software for any purpose, 12 * including commercial applications, and to alter it and redistribute it 13 * freely, subject to the following restrictions: 14 * 15 * 1. The origin of this software must not be misrepresented; you must not 16 * claim that you wrote the original software. If you use this software 17 * in a product, an acknowledgment in the product documentation would be 18 * appreciated but is not required. 19 * 2. Altered source versions must be plainly marked as such, and must not be 20 * misrepresented as being the original software. 21 * 3. This notice may not be removed or altered from any source distribution. 22 * 23 * NOTE: All referenced figures are from 24 * Recommendation ITU-T T.81 (1992) | ISO/IEC 10918-1:1994. 25 */ 26 27 #define JPEG_INTERNALS 28 #include "../../../jinclude.h" 29 #include "../../../jpeglib.h" 30 #include "../../../jsimd.h" 31 #include "../../../jdct.h" 32 #include "../../../jsimddct.h" 33 #include "../../jsimd.h" 34 #include "../align.h" 35 #include "../jchuff.h" 36 #include "neon-compat.h" 37 38 #include <limits.h> 39 40 #include <arm_neon.h> 41 42 43 ALIGN(16) static const uint8_t jsimd_huff_encode_one_block_consts[] = { 44 0, 1, 2, 3, 16, 17, 32, 33, 45 18, 19, 4, 5, 6, 7, 20, 21, 46 34, 35, 48, 49, 255, 255, 50, 51, 47 36, 37, 22, 23, 8, 9, 10, 11, 48 255, 255, 6, 7, 20, 21, 34, 35, 49 48, 49, 255, 255, 50, 51, 36, 37, 50 54, 55, 40, 41, 26, 27, 12, 13, 51 14, 15, 28, 29, 42, 43, 56, 57, 52 6, 7, 20, 21, 34, 35, 48, 49, 53 50, 51, 36, 37, 22, 23, 8, 9, 54 26, 27, 12, 13, 255, 255, 14, 15, 55 28, 29, 42, 43, 56, 57, 255, 255, 56 52, 53, 54, 55, 40, 41, 26, 27, 57 12, 13, 255, 255, 14, 15, 28, 29, 58 26, 27, 40, 41, 42, 43, 28, 29, 59 14, 15, 30, 31, 44, 45, 46, 47 60 }; 61 62 /* The AArch64 implementation of the FLUSH() macro triggers a UBSan misaligned 63 * address warning because the macro sometimes writes a 64-bit value to a 64 * non-64-bit-aligned address. That behavior is technically undefined per 65 * the C specification, but it is supported by the AArch64 architecture and 66 * compilers. 67 */ 68 #if defined(__has_feature) 69 #if __has_feature(undefined_behavior_sanitizer) 70 __attribute__((no_sanitize("alignment"))) 71 #endif 72 #endif 73 JOCTET *jsimd_huff_encode_one_block_neon(void *state, JOCTET *buffer, 74 JCOEFPTR block, int last_dc_val, 75 c_derived_tbl *dctbl, 76 c_derived_tbl *actbl) 77 { 78 uint16_t block_diff[DCTSIZE2]; 79 80 /* Load lookup table indices for rows of zig-zag ordering. */ 81 #ifdef HAVE_VLD1Q_U8_X4 82 const uint8x16x4_t idx_rows_0123 = 83 vld1q_u8_x4(jsimd_huff_encode_one_block_consts + 0 * DCTSIZE); 84 const uint8x16x4_t idx_rows_4567 = 85 vld1q_u8_x4(jsimd_huff_encode_one_block_consts + 8 * DCTSIZE); 86 #else 87 /* GCC does not currently support intrinsics vl1dq_<type>_x4(). */ 88 const uint8x16x4_t idx_rows_0123 = { { 89 vld1q_u8(jsimd_huff_encode_one_block_consts + 0 * DCTSIZE), 90 vld1q_u8(jsimd_huff_encode_one_block_consts + 2 * DCTSIZE), 91 vld1q_u8(jsimd_huff_encode_one_block_consts + 4 * DCTSIZE), 92 vld1q_u8(jsimd_huff_encode_one_block_consts + 6 * DCTSIZE) 93 } }; 94 const uint8x16x4_t idx_rows_4567 = { { 95 vld1q_u8(jsimd_huff_encode_one_block_consts + 8 * DCTSIZE), 96 vld1q_u8(jsimd_huff_encode_one_block_consts + 10 * DCTSIZE), 97 vld1q_u8(jsimd_huff_encode_one_block_consts + 12 * DCTSIZE), 98 vld1q_u8(jsimd_huff_encode_one_block_consts + 14 * DCTSIZE) 99 } }; 100 #endif 101 102 /* Load 8x8 block of DCT coefficients. */ 103 #ifdef HAVE_VLD1Q_U8_X4 104 const int8x16x4_t tbl_rows_0123 = 105 vld1q_s8_x4((int8_t *)(block + 0 * DCTSIZE)); 106 const int8x16x4_t tbl_rows_4567 = 107 vld1q_s8_x4((int8_t *)(block + 4 * DCTSIZE)); 108 #else 109 const int8x16x4_t tbl_rows_0123 = { { 110 vld1q_s8((int8_t *)(block + 0 * DCTSIZE)), 111 vld1q_s8((int8_t *)(block + 1 * DCTSIZE)), 112 vld1q_s8((int8_t *)(block + 2 * DCTSIZE)), 113 vld1q_s8((int8_t *)(block + 3 * DCTSIZE)) 114 } }; 115 const int8x16x4_t tbl_rows_4567 = { { 116 vld1q_s8((int8_t *)(block + 4 * DCTSIZE)), 117 vld1q_s8((int8_t *)(block + 5 * DCTSIZE)), 118 vld1q_s8((int8_t *)(block + 6 * DCTSIZE)), 119 vld1q_s8((int8_t *)(block + 7 * DCTSIZE)) 120 } }; 121 #endif 122 123 /* Initialise extra lookup tables. */ 124 const int8x16x4_t tbl_rows_2345 = { { 125 tbl_rows_0123.val[2], tbl_rows_0123.val[3], 126 tbl_rows_4567.val[0], tbl_rows_4567.val[1] 127 } }; 128 const int8x16x3_t tbl_rows_567 = 129 { { tbl_rows_4567.val[1], tbl_rows_4567.val[2], tbl_rows_4567.val[3] } }; 130 131 /* Shuffle coefficients into zig-zag order. */ 132 int16x8_t row0 = 133 vreinterpretq_s16_s8(vqtbl4q_s8(tbl_rows_0123, idx_rows_0123.val[0])); 134 int16x8_t row1 = 135 vreinterpretq_s16_s8(vqtbl4q_s8(tbl_rows_0123, idx_rows_0123.val[1])); 136 int16x8_t row2 = 137 vreinterpretq_s16_s8(vqtbl4q_s8(tbl_rows_2345, idx_rows_0123.val[2])); 138 int16x8_t row3 = 139 vreinterpretq_s16_s8(vqtbl4q_s8(tbl_rows_0123, idx_rows_0123.val[3])); 140 int16x8_t row4 = 141 vreinterpretq_s16_s8(vqtbl4q_s8(tbl_rows_4567, idx_rows_4567.val[0])); 142 int16x8_t row5 = 143 vreinterpretq_s16_s8(vqtbl4q_s8(tbl_rows_2345, idx_rows_4567.val[1])); 144 int16x8_t row6 = 145 vreinterpretq_s16_s8(vqtbl4q_s8(tbl_rows_4567, idx_rows_4567.val[2])); 146 int16x8_t row7 = 147 vreinterpretq_s16_s8(vqtbl3q_s8(tbl_rows_567, idx_rows_4567.val[3])); 148 149 /* Compute DC coefficient difference value (F.1.1.5.1). */ 150 row0 = vsetq_lane_s16(block[0] - last_dc_val, row0, 0); 151 /* Initialize AC coefficient lanes not reachable by lookup tables. */ 152 row1 = 153 vsetq_lane_s16(vgetq_lane_s16(vreinterpretq_s16_s8(tbl_rows_4567.val[0]), 154 0), row1, 2); 155 row2 = 156 vsetq_lane_s16(vgetq_lane_s16(vreinterpretq_s16_s8(tbl_rows_0123.val[1]), 157 4), row2, 0); 158 row2 = 159 vsetq_lane_s16(vgetq_lane_s16(vreinterpretq_s16_s8(tbl_rows_4567.val[2]), 160 0), row2, 5); 161 row5 = 162 vsetq_lane_s16(vgetq_lane_s16(vreinterpretq_s16_s8(tbl_rows_0123.val[1]), 163 7), row5, 2); 164 row5 = 165 vsetq_lane_s16(vgetq_lane_s16(vreinterpretq_s16_s8(tbl_rows_4567.val[2]), 166 3), row5, 7); 167 row6 = 168 vsetq_lane_s16(vgetq_lane_s16(vreinterpretq_s16_s8(tbl_rows_0123.val[3]), 169 7), row6, 5); 170 171 /* DCT block is now in zig-zag order; start Huffman encoding process. */ 172 173 /* Construct bitmap to accelerate encoding of AC coefficients. A set bit 174 * means that the corresponding coefficient != 0. 175 */ 176 uint16x8_t row0_ne_0 = vtstq_s16(row0, row0); 177 uint16x8_t row1_ne_0 = vtstq_s16(row1, row1); 178 uint16x8_t row2_ne_0 = vtstq_s16(row2, row2); 179 uint16x8_t row3_ne_0 = vtstq_s16(row3, row3); 180 uint16x8_t row4_ne_0 = vtstq_s16(row4, row4); 181 uint16x8_t row5_ne_0 = vtstq_s16(row5, row5); 182 uint16x8_t row6_ne_0 = vtstq_s16(row6, row6); 183 uint16x8_t row7_ne_0 = vtstq_s16(row7, row7); 184 185 uint8x16_t row10_ne_0 = vuzp1q_u8(vreinterpretq_u8_u16(row1_ne_0), 186 vreinterpretq_u8_u16(row0_ne_0)); 187 uint8x16_t row32_ne_0 = vuzp1q_u8(vreinterpretq_u8_u16(row3_ne_0), 188 vreinterpretq_u8_u16(row2_ne_0)); 189 uint8x16_t row54_ne_0 = vuzp1q_u8(vreinterpretq_u8_u16(row5_ne_0), 190 vreinterpretq_u8_u16(row4_ne_0)); 191 uint8x16_t row76_ne_0 = vuzp1q_u8(vreinterpretq_u8_u16(row7_ne_0), 192 vreinterpretq_u8_u16(row6_ne_0)); 193 194 /* { 0x80, 0x40, 0x20, 0x10, 0x08, 0x04, 0x02, 0x01 } */ 195 const uint8x16_t bitmap_mask = 196 vreinterpretq_u8_u64(vdupq_n_u64(0x0102040810204080)); 197 198 uint8x16_t bitmap_rows_10 = vandq_u8(row10_ne_0, bitmap_mask); 199 uint8x16_t bitmap_rows_32 = vandq_u8(row32_ne_0, bitmap_mask); 200 uint8x16_t bitmap_rows_54 = vandq_u8(row54_ne_0, bitmap_mask); 201 uint8x16_t bitmap_rows_76 = vandq_u8(row76_ne_0, bitmap_mask); 202 203 uint8x16_t bitmap_rows_3210 = vpaddq_u8(bitmap_rows_32, bitmap_rows_10); 204 uint8x16_t bitmap_rows_7654 = vpaddq_u8(bitmap_rows_76, bitmap_rows_54); 205 uint8x16_t bitmap_rows_76543210 = vpaddq_u8(bitmap_rows_7654, 206 bitmap_rows_3210); 207 uint8x8_t bitmap_all = vpadd_u8(vget_low_u8(bitmap_rows_76543210), 208 vget_high_u8(bitmap_rows_76543210)); 209 210 /* Shift left to remove DC bit. */ 211 bitmap_all = 212 vreinterpret_u8_u64(vshl_n_u64(vreinterpret_u64_u8(bitmap_all), 1)); 213 /* Count bits set (number of non-zero coefficients) in bitmap. */ 214 unsigned int non_zero_coefficients = vaddv_u8(vcnt_u8(bitmap_all)); 215 /* Move bitmap to 64-bit scalar register. */ 216 uint64_t bitmap = vget_lane_u64(vreinterpret_u64_u8(bitmap_all), 0); 217 218 /* Set up state and bit buffer for output bitstream. */ 219 working_state *state_ptr = (working_state *)state; 220 int free_bits = state_ptr->cur.free_bits; 221 size_t put_buffer = state_ptr->cur.put_buffer; 222 223 /* Encode DC coefficient. */ 224 225 /* For negative coeffs: diff = abs(coeff) -1 = ~abs(coeff) */ 226 int16x8_t abs_row0 = vabsq_s16(row0); 227 int16x8_t row0_lz = vclzq_s16(abs_row0); 228 uint16x8_t row0_mask = vshlq_u16(vcltzq_s16(row0), vnegq_s16(row0_lz)); 229 uint16x8_t row0_diff = veorq_u16(vreinterpretq_u16_s16(abs_row0), row0_mask); 230 /* Find nbits required to specify sign and amplitude of coefficient. */ 231 unsigned int lz = vgetq_lane_u16(vreinterpretq_u16_s16(row0_lz), 0); 232 unsigned int nbits = 16 - lz; 233 /* Emit Huffman-coded symbol and additional diff bits. */ 234 unsigned int diff = vgetq_lane_u16(row0_diff, 0); 235 PUT_CODE(dctbl->ehufco[nbits], dctbl->ehufsi[nbits], diff) 236 237 /* Encode AC coefficients. */ 238 239 unsigned int r = 0; /* r = run length of zeros */ 240 unsigned int i = 1; /* i = number of coefficients encoded */ 241 /* Code and size information for a run length of 16 zero coefficients */ 242 const unsigned int code_0xf0 = actbl->ehufco[0xf0]; 243 const unsigned int size_0xf0 = actbl->ehufsi[0xf0]; 244 245 /* The most efficient method of computing nbits and diff depends on the 246 * number of non-zero coefficients. If the bitmap is not too sparse (> 8 247 * non-zero AC coefficients), it is beneficial to do all of the work using 248 * Neon; else we do some of the work using Neon and the rest on demand using 249 * scalar code. 250 */ 251 if (non_zero_coefficients > 8) { 252 uint8_t block_nbits[DCTSIZE2]; 253 254 int16x8_t abs_row1 = vabsq_s16(row1); 255 int16x8_t abs_row2 = vabsq_s16(row2); 256 int16x8_t abs_row3 = vabsq_s16(row3); 257 int16x8_t abs_row4 = vabsq_s16(row4); 258 int16x8_t abs_row5 = vabsq_s16(row5); 259 int16x8_t abs_row6 = vabsq_s16(row6); 260 int16x8_t abs_row7 = vabsq_s16(row7); 261 int16x8_t row1_lz = vclzq_s16(abs_row1); 262 int16x8_t row2_lz = vclzq_s16(abs_row2); 263 int16x8_t row3_lz = vclzq_s16(abs_row3); 264 int16x8_t row4_lz = vclzq_s16(abs_row4); 265 int16x8_t row5_lz = vclzq_s16(abs_row5); 266 int16x8_t row6_lz = vclzq_s16(abs_row6); 267 int16x8_t row7_lz = vclzq_s16(abs_row7); 268 /* Narrow leading zero count to 8 bits. */ 269 uint8x16_t row01_lz = vuzp1q_u8(vreinterpretq_u8_s16(row0_lz), 270 vreinterpretq_u8_s16(row1_lz)); 271 uint8x16_t row23_lz = vuzp1q_u8(vreinterpretq_u8_s16(row2_lz), 272 vreinterpretq_u8_s16(row3_lz)); 273 uint8x16_t row45_lz = vuzp1q_u8(vreinterpretq_u8_s16(row4_lz), 274 vreinterpretq_u8_s16(row5_lz)); 275 uint8x16_t row67_lz = vuzp1q_u8(vreinterpretq_u8_s16(row6_lz), 276 vreinterpretq_u8_s16(row7_lz)); 277 /* Compute nbits needed to specify magnitude of each coefficient. */ 278 uint8x16_t row01_nbits = vsubq_u8(vdupq_n_u8(16), row01_lz); 279 uint8x16_t row23_nbits = vsubq_u8(vdupq_n_u8(16), row23_lz); 280 uint8x16_t row45_nbits = vsubq_u8(vdupq_n_u8(16), row45_lz); 281 uint8x16_t row67_nbits = vsubq_u8(vdupq_n_u8(16), row67_lz); 282 /* Store nbits. */ 283 vst1q_u8(block_nbits + 0 * DCTSIZE, row01_nbits); 284 vst1q_u8(block_nbits + 2 * DCTSIZE, row23_nbits); 285 vst1q_u8(block_nbits + 4 * DCTSIZE, row45_nbits); 286 vst1q_u8(block_nbits + 6 * DCTSIZE, row67_nbits); 287 /* Mask bits not required to specify sign and amplitude of diff. */ 288 uint16x8_t row1_mask = vshlq_u16(vcltzq_s16(row1), vnegq_s16(row1_lz)); 289 uint16x8_t row2_mask = vshlq_u16(vcltzq_s16(row2), vnegq_s16(row2_lz)); 290 uint16x8_t row3_mask = vshlq_u16(vcltzq_s16(row3), vnegq_s16(row3_lz)); 291 uint16x8_t row4_mask = vshlq_u16(vcltzq_s16(row4), vnegq_s16(row4_lz)); 292 uint16x8_t row5_mask = vshlq_u16(vcltzq_s16(row5), vnegq_s16(row5_lz)); 293 uint16x8_t row6_mask = vshlq_u16(vcltzq_s16(row6), vnegq_s16(row6_lz)); 294 uint16x8_t row7_mask = vshlq_u16(vcltzq_s16(row7), vnegq_s16(row7_lz)); 295 /* diff = abs(coeff) ^ sign(coeff) [no-op for positive coefficients] */ 296 uint16x8_t row1_diff = veorq_u16(vreinterpretq_u16_s16(abs_row1), 297 row1_mask); 298 uint16x8_t row2_diff = veorq_u16(vreinterpretq_u16_s16(abs_row2), 299 row2_mask); 300 uint16x8_t row3_diff = veorq_u16(vreinterpretq_u16_s16(abs_row3), 301 row3_mask); 302 uint16x8_t row4_diff = veorq_u16(vreinterpretq_u16_s16(abs_row4), 303 row4_mask); 304 uint16x8_t row5_diff = veorq_u16(vreinterpretq_u16_s16(abs_row5), 305 row5_mask); 306 uint16x8_t row6_diff = veorq_u16(vreinterpretq_u16_s16(abs_row6), 307 row6_mask); 308 uint16x8_t row7_diff = veorq_u16(vreinterpretq_u16_s16(abs_row7), 309 row7_mask); 310 /* Store diff bits. */ 311 vst1q_u16(block_diff + 0 * DCTSIZE, row0_diff); 312 vst1q_u16(block_diff + 1 * DCTSIZE, row1_diff); 313 vst1q_u16(block_diff + 2 * DCTSIZE, row2_diff); 314 vst1q_u16(block_diff + 3 * DCTSIZE, row3_diff); 315 vst1q_u16(block_diff + 4 * DCTSIZE, row4_diff); 316 vst1q_u16(block_diff + 5 * DCTSIZE, row5_diff); 317 vst1q_u16(block_diff + 6 * DCTSIZE, row6_diff); 318 vst1q_u16(block_diff + 7 * DCTSIZE, row7_diff); 319 320 while (bitmap != 0) { 321 r = BUILTIN_CLZLL(bitmap); 322 i += r; 323 bitmap <<= r; 324 nbits = block_nbits[i]; 325 diff = block_diff[i]; 326 while (r > 15) { 327 /* If run length > 15, emit special run-length-16 codes. */ 328 PUT_BITS(code_0xf0, size_0xf0) 329 r -= 16; 330 } 331 /* Emit Huffman symbol for run length / number of bits. (F.1.2.2.1) */ 332 unsigned int rs = (r << 4) + nbits; 333 PUT_CODE(actbl->ehufco[rs], actbl->ehufsi[rs], diff) 334 i++; 335 bitmap <<= 1; 336 } 337 } else if (bitmap != 0) { 338 uint16_t block_abs[DCTSIZE2]; 339 /* Compute and store absolute value of coefficients. */ 340 int16x8_t abs_row1 = vabsq_s16(row1); 341 int16x8_t abs_row2 = vabsq_s16(row2); 342 int16x8_t abs_row3 = vabsq_s16(row3); 343 int16x8_t abs_row4 = vabsq_s16(row4); 344 int16x8_t abs_row5 = vabsq_s16(row5); 345 int16x8_t abs_row6 = vabsq_s16(row6); 346 int16x8_t abs_row7 = vabsq_s16(row7); 347 vst1q_u16(block_abs + 0 * DCTSIZE, vreinterpretq_u16_s16(abs_row0)); 348 vst1q_u16(block_abs + 1 * DCTSIZE, vreinterpretq_u16_s16(abs_row1)); 349 vst1q_u16(block_abs + 2 * DCTSIZE, vreinterpretq_u16_s16(abs_row2)); 350 vst1q_u16(block_abs + 3 * DCTSIZE, vreinterpretq_u16_s16(abs_row3)); 351 vst1q_u16(block_abs + 4 * DCTSIZE, vreinterpretq_u16_s16(abs_row4)); 352 vst1q_u16(block_abs + 5 * DCTSIZE, vreinterpretq_u16_s16(abs_row5)); 353 vst1q_u16(block_abs + 6 * DCTSIZE, vreinterpretq_u16_s16(abs_row6)); 354 vst1q_u16(block_abs + 7 * DCTSIZE, vreinterpretq_u16_s16(abs_row7)); 355 /* Compute diff bits (without nbits mask) and store. */ 356 uint16x8_t row1_diff = veorq_u16(vreinterpretq_u16_s16(abs_row1), 357 vcltzq_s16(row1)); 358 uint16x8_t row2_diff = veorq_u16(vreinterpretq_u16_s16(abs_row2), 359 vcltzq_s16(row2)); 360 uint16x8_t row3_diff = veorq_u16(vreinterpretq_u16_s16(abs_row3), 361 vcltzq_s16(row3)); 362 uint16x8_t row4_diff = veorq_u16(vreinterpretq_u16_s16(abs_row4), 363 vcltzq_s16(row4)); 364 uint16x8_t row5_diff = veorq_u16(vreinterpretq_u16_s16(abs_row5), 365 vcltzq_s16(row5)); 366 uint16x8_t row6_diff = veorq_u16(vreinterpretq_u16_s16(abs_row6), 367 vcltzq_s16(row6)); 368 uint16x8_t row7_diff = veorq_u16(vreinterpretq_u16_s16(abs_row7), 369 vcltzq_s16(row7)); 370 vst1q_u16(block_diff + 0 * DCTSIZE, row0_diff); 371 vst1q_u16(block_diff + 1 * DCTSIZE, row1_diff); 372 vst1q_u16(block_diff + 2 * DCTSIZE, row2_diff); 373 vst1q_u16(block_diff + 3 * DCTSIZE, row3_diff); 374 vst1q_u16(block_diff + 4 * DCTSIZE, row4_diff); 375 vst1q_u16(block_diff + 5 * DCTSIZE, row5_diff); 376 vst1q_u16(block_diff + 6 * DCTSIZE, row6_diff); 377 vst1q_u16(block_diff + 7 * DCTSIZE, row7_diff); 378 379 /* Same as above but must mask diff bits and compute nbits on demand. */ 380 while (bitmap != 0) { 381 r = BUILTIN_CLZLL(bitmap); 382 i += r; 383 bitmap <<= r; 384 lz = BUILTIN_CLZ(block_abs[i]); 385 nbits = 32 - lz; 386 diff = ((unsigned int)block_diff[i] << lz) >> lz; 387 while (r > 15) { 388 /* If run length > 15, emit special run-length-16 codes. */ 389 PUT_BITS(code_0xf0, size_0xf0) 390 r -= 16; 391 } 392 /* Emit Huffman symbol for run length / number of bits. (F.1.2.2.1) */ 393 unsigned int rs = (r << 4) + nbits; 394 PUT_CODE(actbl->ehufco[rs], actbl->ehufsi[rs], diff) 395 i++; 396 bitmap <<= 1; 397 } 398 } 399 400 /* If the last coefficient(s) were zero, emit an end-of-block (EOB) code. 401 * The value of RS for the EOB code is 0. 402 */ 403 if (i != 64) { 404 PUT_BITS(actbl->ehufco[0], actbl->ehufsi[0]) 405 } 406 407 state_ptr->cur.put_buffer = put_buffer; 408 state_ptr->cur.free_bits = free_bits; 409 410 return buffer; 411 }