Encoding-x86-shared.h (13211B)
1 /* -*- Mode: C++; tab-width: 8; indent-tabs-mode: nil; c-basic-offset: 2 -*- 2 * vim: set ts=8 sts=2 et sw=2 tw=80: 3 * This Source Code Form is subject to the terms of the Mozilla Public 4 * License, v. 2.0. If a copy of the MPL was not distributed with this 5 * file, You can obtain one at http://mozilla.org/MPL/2.0/. */ 6 7 #ifndef jit_x86_shared_Encoding_x86_shared_h 8 #define jit_x86_shared_Encoding_x86_shared_h 9 10 #include <type_traits> 11 12 #include "jit/x86-shared/Constants-x86-shared.h" 13 14 namespace js { 15 namespace jit { 16 17 namespace X86Encoding { 18 19 static const size_t MaxInstructionSize = 16; 20 21 // These enumerated values are following the Intel documentation Volume 2C [1], 22 // Appendix A.2 and Appendix A.3. 23 // 24 // Operand size/types as listed in the Appendix A.2. Tables of the instructions 25 // and their operands can be found in the Appendix A.3. 26 // 27 // B = reg (VEX.vvvv of VEX prefix) 28 // E = reg/mem 29 // G = reg (reg field of ModR/M) 30 // U = xmm (R/M field of ModR/M) 31 // V = xmm (reg field of ModR/M) 32 // W = xmm/mem64 33 // I = immediate 34 // O = offset 35 // 36 // b = byte (8-bit) 37 // w = word (16-bit) 38 // v = register size 39 // d = double (32-bit) 40 // dq = double-quad (128-bit) (xmm) 41 // ss = scalar float 32 (xmm) 42 // ps = packed float 32 (xmm) 43 // sd = scalar double (xmm) 44 // pd = packed double (xmm) 45 // y = 32/64-bit 46 // z = 16/32/64-bit 47 // vqp = (*) 48 // 49 // (*) Some website [2] provides a convenient list of all instructions, but be 50 // aware that they do not follow the Intel documentation naming, as the 51 // following enumeration does. Do not use these names as a reference for adding 52 // new instructions. 53 // 54 // [1] 55 // http://www.intel.com/content/www/us/en/architecture-and-technology/64-ia-32-architectures-software-developer-manual-325462.html 56 // [2] http://ref.x86asm.net/geek.html 57 // 58 // OPn_NAME_DstSrc 59 enum OneByteOpcodeID { 60 OP_NOP_00 = 0x00, 61 OP_ADD_EbGb = 0x00, 62 OP_ADD_EvGv = 0x01, 63 OP_ADD_GvEv = 0x03, 64 OP_ADD_EAXIv = 0x05, 65 OP_OR_EbGb = 0x08, 66 OP_OR_EvGv = 0x09, 67 OP_OR_GvEv = 0x0B, 68 OP_OR_EAXIv = 0x0D, 69 OP_2BYTE_ESCAPE = 0x0F, 70 OP_NOP_0F = 0x0F, 71 OP_ADC_GvEv = 0x13, 72 OP_SBB_GvEv = 0x1B, 73 OP_NOP_1F = 0x1F, 74 OP_AND_EbGb = 0x20, 75 OP_AND_EvGv = 0x21, 76 OP_AND_GvEv = 0x23, 77 OP_AND_EAXIv = 0x25, 78 OP_SUB_EbGb = 0x28, 79 OP_SUB_EvGv = 0x29, 80 OP_SUB_GvEv = 0x2B, 81 OP_SUB_EAXIv = 0x2D, 82 PRE_PREDICT_BRANCH_NOT_TAKEN = 0x2E, 83 OP_XOR_EbGb = 0x30, 84 OP_XOR_EvGv = 0x31, 85 OP_XOR_GvEv = 0x33, 86 OP_XOR_EAXIv = 0x35, 87 OP_CMP_EbGb = 0x38, 88 OP_CMP_EvGv = 0x39, 89 OP_CMP_GbEb = 0x3A, 90 OP_CMP_GvEv = 0x3B, 91 OP_CMP_EAXIb = 0x3C, 92 OP_CMP_EAXIv = 0x3D, 93 #ifdef JS_CODEGEN_X64 94 PRE_REX = 0x40, 95 #endif 96 OP_NOP_40 = 0x40, 97 OP_NOP_44 = 0x44, 98 OP_PUSH_EAX = 0x50, 99 OP_POP_EAX = 0x58, 100 #ifdef JS_CODEGEN_X86 101 OP_PUSHA = 0x60, 102 OP_POPA = 0x61, 103 #endif 104 #ifdef JS_CODEGEN_X64 105 OP_MOVSXD_GvEv = 0x63, 106 #endif 107 PRE_OPERAND_SIZE = 0x66, 108 PRE_SSE_66 = 0x66, 109 OP_NOP_66 = 0x66, 110 OP_PUSH_Iz = 0x68, 111 OP_IMUL_GvEvIz = 0x69, 112 OP_PUSH_Ib = 0x6a, 113 OP_IMUL_GvEvIb = 0x6b, 114 OP_JCC_rel8 = 0x70, 115 OP_GROUP1_EbIb = 0x80, 116 OP_NOP_80 = 0x80, 117 OP_GROUP1_EvIz = 0x81, 118 OP_GROUP1_EvIb = 0x83, 119 OP_TEST_EbGb = 0x84, 120 OP_NOP_84 = 0x84, 121 OP_TEST_EvGv = 0x85, 122 OP_XCHG_GbEb = 0x86, 123 OP_XCHG_GvEv = 0x87, 124 OP_MOV_EbGv = 0x88, 125 OP_MOV_EvGv = 0x89, 126 OP_MOV_GvEb = 0x8A, 127 OP_MOV_GvEv = 0x8B, 128 OP_LEA = 0x8D, 129 OP_GROUP1A_Ev = 0x8F, 130 OP_NOP = 0x90, 131 OP_PUSHFLAGS = 0x9C, 132 OP_POPFLAGS = 0x9D, 133 OP_CDQ = 0x99, 134 OP_MOV_EAXOv = 0xA1, 135 OP_MOV_OvEAX = 0xA3, 136 OP_TEST_EAXIb = 0xA8, 137 OP_TEST_EAXIv = 0xA9, 138 OP_MOV_EbIb = 0xB0, 139 OP_MOV_EAXIv = 0xB8, 140 OP_GROUP2_EvIb = 0xC1, 141 OP_ADDP_ST0_ST1 = 0xC1, 142 OP_RET_Iz = 0xC2, 143 PRE_VEX_C4 = 0xC4, 144 PRE_VEX_C5 = 0xC5, 145 OP_RET = 0xC3, 146 OP_GROUP11_EvIb = 0xC6, 147 OP_GROUP11_EvIz = 0xC7, 148 OP_INT3 = 0xCC, 149 OP_GROUP2_Ev1 = 0xD1, 150 OP_GROUP2_EvCL = 0xD3, 151 OP_FPU6 = 0xDD, 152 OP_FPU6_F32 = 0xD9, 153 OP_FPU6_ADDP = 0xDE, 154 OP_FILD = 0xDF, 155 OP_CALL_rel32 = 0xE8, 156 OP_JMP_rel32 = 0xE9, 157 OP_JMP_rel8 = 0xEB, 158 PRE_LOCK = 0xF0, 159 PRE_SSE_F2 = 0xF2, 160 PRE_SSE_F3 = 0xF3, 161 PRE_REP = 0xF3, 162 OP_HLT = 0xF4, 163 OP_GROUP3_EbIb = 0xF6, 164 OP_GROUP3_Ev = 0xF7, 165 OP_GROUP3_EvIz = 166 0xF7, // OP_GROUP3_Ev has an immediate, when instruction is a test. 167 OP_GROUP5_Ev = 0xFF 168 }; 169 170 enum class ShiftID { 171 vpsrlx = 2, 172 vpsrldq = 3, 173 vpsrad = 4, 174 vpsllx = 6, 175 vpslldq = 7 176 }; 177 178 enum TwoByteOpcodeID { 179 OP2_UD2 = 0x0B, 180 OP2_MOVSD_VsdWsd = 0x10, 181 OP2_MOVPS_VpsWps = 0x10, 182 OP2_MOVSD_WsdVsd = 0x11, 183 OP2_MOVPS_WpsVps = 0x11, 184 OP2_MOVDDUP_VqWq = 0x12, 185 OP2_MOVHLPS_VqUq = 0x12, 186 OP2_MOVSLDUP_VpsWps = 0x12, 187 OP2_MOVLPS_VqEq = 0x12, 188 OP2_MOVLPS_EqVq = 0x13, 189 OP2_UNPCKLPS_VsdWsd = 0x14, 190 OP2_UNPCKHPS_VsdWsd = 0x15, 191 OP2_MOVLHPS_VqUq = 0x16, 192 OP2_MOVSHDUP_VpsWps = 0x16, 193 OP2_MOVHPS_VqEq = 0x16, 194 OP2_MOVHPS_EqVq = 0x17, 195 OP2_MOVAPD_VsdWsd = 0x28, 196 OP2_MOVAPS_VsdWsd = 0x28, 197 OP2_MOVAPS_WsdVsd = 0x29, 198 OP2_CVTSI2SD_VsdEd = 0x2A, 199 OP2_CVTTSD2SI_GdWsd = 0x2C, 200 OP2_UCOMISD_VsdWsd = 0x2E, 201 OP2_CMOVCC_GvEv = 0x40, 202 OP2_MOVMSKPD_EdVd = 0x50, 203 OP2_ANDPS_VpsWps = 0x54, 204 OP2_ANDNPS_VpsWps = 0x55, 205 OP2_ORPS_VpsWps = 0x56, 206 OP2_XORPS_VpsWps = 0x57, 207 OP2_ADDSD_VsdWsd = 0x58, 208 OP2_ADDPS_VpsWps = 0x58, 209 OP2_ADDPD_VpdWpd = 0x58, 210 OP2_MULSD_VsdWsd = 0x59, 211 OP2_MULPD_VpdWpd = 0x59, 212 OP2_MULPS_VpsWps = 0x59, 213 OP2_CVTSS2SD_VsdEd = 0x5A, 214 OP2_CVTSD2SS_VsdEd = 0x5A, 215 OP2_CVTPS2PD_VpdWps = 0x5A, 216 OP2_CVTPD2PS_VpsWpd = 0x5A, 217 OP2_CVTTPS2DQ_VdqWps = 0x5B, 218 OP2_CVTDQ2PS_VpsWdq = 0x5B, 219 OP2_SUBSD_VsdWsd = 0x5C, 220 OP2_SUBPS_VpsWps = 0x5C, 221 OP2_SUBPD_VpdWpd = 0x5C, 222 OP2_MINSD_VsdWsd = 0x5D, 223 OP2_MINSS_VssWss = 0x5D, 224 OP2_MINPS_VpsWps = 0x5D, 225 OP2_MINPD_VpdWpd = 0x5D, 226 OP2_DIVSD_VsdWsd = 0x5E, 227 OP2_DIVPS_VpsWps = 0x5E, 228 OP2_DIVPD_VpdWpd = 0x5E, 229 OP2_MAXSD_VsdWsd = 0x5F, 230 OP2_MAXSS_VssWss = 0x5F, 231 OP2_MAXPS_VpsWps = 0x5F, 232 OP2_MAXPD_VpdWpd = 0x5F, 233 OP2_SQRTSD_VsdWsd = 0x51, 234 OP2_SQRTSS_VssWss = 0x51, 235 OP2_SQRTPS_VpsWps = 0x51, 236 OP2_SQRTPD_VpdWpd = 0x51, 237 OP2_RSQRTPS_VpsWps = 0x52, 238 OP2_RCPPS_VpsWps = 0x53, 239 OP2_ANDPD_VpdWpd = 0x54, 240 OP2_ORPD_VpdWpd = 0x56, 241 OP2_XORPD_VpdWpd = 0x57, 242 OP2_PUNPCKLBW_VdqWdq = 0x60, 243 OP2_PUNPCKLWD_VdqWdq = 0x61, 244 OP2_PUNPCKLDQ_VdqWdq = 0x62, 245 OP2_PACKSSWB_VdqWdq = 0x63, 246 OP2_PCMPGTB_VdqWdq = 0x64, 247 OP2_PCMPGTW_VdqWdq = 0x65, 248 OP2_PCMPGTD_VdqWdq = 0x66, 249 OP2_PACKUSWB_VdqWdq = 0x67, 250 OP2_PUNPCKHBW_VdqWdq = 0x68, 251 OP2_PUNPCKHWD_VdqWdq = 0x69, 252 OP2_PUNPCKHDQ_VdqWdq = 0x6A, 253 OP2_PACKSSDW_VdqWdq = 0x6B, 254 OP2_PUNPCKLQDQ_VdqWdq = 0x6C, 255 OP2_PUNPCKHQDQ_VdqWdq = 0x6D, 256 OP2_MOVD_VdEd = 0x6E, 257 OP2_MOVDQ_VsdWsd = 0x6F, 258 OP2_MOVDQ_VdqWdq = 0x6F, 259 OP2_PSHUFD_VdqWdqIb = 0x70, 260 OP2_PSHUFLW_VdqWdqIb = 0x70, 261 OP2_PSHUFHW_VdqWdqIb = 0x70, 262 OP2_PSLLW_UdqIb = 0x71, 263 OP2_PSRAW_UdqIb = 0x71, 264 OP2_PSRLW_UdqIb = 0x71, 265 OP2_PSLLD_UdqIb = 0x72, 266 OP2_PSRAD_UdqIb = 0x72, 267 OP2_PSRLD_UdqIb = 0x72, 268 OP2_PSRLDQ_Vd = 0x73, 269 OP2_PCMPEQB_VdqWdq = 0x74, 270 OP2_PCMPEQW_VdqWdq = 0x75, 271 OP2_PCMPEQD_VdqWdq = 0x76, 272 OP2_HADDPD = 0x7C, 273 OP2_MOVD_EdVd = 0x7E, 274 OP2_MOVQ_VdWd = 0x7E, 275 OP2_MOVDQ_WdqVdq = 0x7F, 276 OP2_JCC_rel32 = 0x80, 277 OP_SETCC = 0x90, 278 OP2_SHLD = 0xA4, 279 OP2_SHLD_GvEv = 0xA5, 280 OP2_SHRD = 0xAC, 281 OP2_SHRD_GvEv = 0xAD, 282 OP_FENCE = 0xAE, 283 OP2_IMUL_GvEv = 0xAF, 284 OP2_CMPXCHG_GvEb = 0xB0, 285 OP2_CMPXCHG_GvEw = 0xB1, 286 OP2_POPCNT_GvEv = 0xB8, 287 OP2_BSF_GvEv = 0xBC, 288 OP2_TZCNT_GvEv = 0xBC, 289 OP2_BSR_GvEv = 0xBD, 290 OP2_LZCNT_GvEv = 0xBD, 291 OP2_MOVSX_GvEb = 0xBE, 292 OP2_MOVSX_GvEw = 0xBF, 293 OP2_MOVZX_GvEb = 0xB6, 294 OP2_MOVZX_GvEw = 0xB7, 295 OP2_XADD_EbGb = 0xC0, 296 OP2_XADD_EvGv = 0xC1, 297 OP2_CMPPS_VpsWps = 0xC2, 298 OP2_CMPPD_VpdWpd = 0xC2, 299 OP2_PINSRW = 0xC4, 300 OP2_PEXTRW_GdUdIb = 0xC5, 301 OP2_SHUFPS_VpsWpsIb = 0xC6, 302 OP2_SHUFPD_VpdWpdIb = 0xC6, 303 OP2_CMPXCHGNB = 0xC7, // CMPXCHG8B; CMPXCHG16B with REX 304 OP2_BSWAP = 0xC8, 305 OP2_PSRLW_VdqWdq = 0xD1, 306 OP2_PSRLD_VdqWdq = 0xD2, 307 OP2_PSRLQ_VdqWdq = 0xD3, 308 OP2_PADDQ_VdqWdq = 0xD4, 309 OP2_PMULLW_VdqWdq = 0xD5, 310 OP2_MOVQ_WdVd = 0xD6, 311 OP2_PMOVMSKB_EdVd = 0xD7, 312 OP2_PSUBUSB_VdqWdq = 0xD8, 313 OP2_PSUBUSW_VdqWdq = 0xD9, 314 OP2_PMINUB_VdqWdq = 0xDA, 315 OP2_PANDDQ_VdqWdq = 0xDB, 316 OP2_PADDUSB_VdqWdq = 0xDC, 317 OP2_PADDUSW_VdqWdq = 0xDD, 318 OP2_PMAXUB_VdqWdq = 0xDE, 319 OP2_PANDNDQ_VdqWdq = 0xDF, 320 OP2_PAVGB_VdqWdq = 0xE0, 321 OP2_PSRAW_VdqWdq = 0xE1, 322 OP2_PSRAD_VdqWdq = 0xE2, 323 OP2_PAVGW_VdqWdq = 0xE3, 324 OP2_PMULHUW_VdqWdq = 0xE4, 325 OP2_PMULHW_VdqWdq = 0xE5, 326 OP2_CVTDQ2PD_VpdWdq = 0xE6, 327 OP2_CVTTPD2DQ_VdqWpd = 0xE6, 328 OP2_PSUBSB_VdqWdq = 0xE8, 329 OP2_PSUBSW_VdqWdq = 0xE9, 330 OP2_PMINSW_VdqWdq = 0xEA, 331 OP2_PORDQ_VdqWdq = 0xEB, 332 OP2_PADDSB_VdqWdq = 0xEC, 333 OP2_PADDSW_VdqWdq = 0xED, 334 OP2_PMAXSW_VdqWdq = 0xEE, 335 OP2_PXORDQ_VdqWdq = 0xEF, 336 OP2_PSLLW_VdqWdq = 0xF1, 337 OP2_PSLLD_VdqWdq = 0xF2, 338 OP2_PSLLQ_VdqWdq = 0xF3, 339 OP2_PMULUDQ_VdqWdq = 0xF4, 340 OP2_PMADDWD_VdqWdq = 0xF5, 341 OP2_PSUBB_VdqWdq = 0xF8, 342 OP2_PSUBW_VdqWdq = 0xF9, 343 OP2_PSUBD_VdqWdq = 0xFA, 344 OP2_PSUBQ_VdqWdq = 0xFB, 345 OP2_PADDB_VdqWdq = 0xFC, 346 OP2_PADDW_VdqWdq = 0xFD, 347 OP2_PADDD_VdqWdq = 0xFE 348 }; 349 350 enum ThreeByteOpcodeID { 351 OP3_PSHUFB_VdqWdq = 0x00, 352 OP3_PHADDD_VdqWdq = 0x02, 353 OP3_PMADDUBSW_VdqWdq = 0x04, 354 OP3_ROUNDPS_VpsWps = 0x08, 355 OP3_ROUNDPD_VpdWpd = 0x09, 356 OP3_ROUNDSS_VsdWsd = 0x0A, 357 OP3_PSIGND_PdqQdq = 0x0A, 358 OP3_ROUNDSD_VsdWsd = 0x0B, 359 OP3_PMULHRSW_VdqWdq = 0x0B, 360 OP3_BLENDPS_VpsWpsIb = 0x0C, 361 OP3_PBLENDW_VdqWdqIb = 0x0E, 362 OP3_PALIGNR_VdqWdqIb = 0x0F, 363 OP3_PBLENDVB_VdqWdq = 0x10, 364 OP3_VCVTPH2PS_VxWxIb = 0x13, 365 OP3_BLENDVPS_VdqWdq = 0x14, 366 OP3_PEXTRB_EvVdqIb = 0x14, 367 OP3_PEXTRW_EwVdqIb = 0x15, 368 OP3_BLENDVPD_VdqWdq = 0x15, 369 OP3_PEXTRD_EvVdqIb = 0x16, 370 OP3_PEXTRQ_EvVdqIb = 0x16, 371 OP3_PTEST_VdVd = 0x17, 372 OP3_EXTRACTPS_EdVdqIb = 0x17, 373 OP3_VBROADCASTSS_VxWd = 0x18, 374 OP3_PABSB_VdqWdq = 0x1C, 375 OP3_PABSW_VdqWdq = 0x1D, 376 OP3_VCVTPS2PH_WxVxIb = 0x1D, 377 OP3_PABSD_VdqWdq = 0x1E, 378 OP3_PINSRB_VdqEvIb = 0x20, 379 OP3_PMOVSXBW_VdqWdq = 0x20, 380 OP3_INSERTPS_VpsUps = 0x21, 381 OP3_PINSRD_VdqEvIb = 0x22, 382 OP3_PINSRQ_VdqEvIb = 0x22, 383 OP3_PMOVSXWD_VdqWdq = 0x23, 384 OP3_PMOVSXDQ_VdqWdq = 0x25, 385 OP3_PMULDQ_VdqWdq = 0x28, 386 OP3_PCMPEQQ_VdqWdq = 0x29, 387 OP3_PACKUSDW_VdqWdq = 0x2B, 388 OP3_PMOVZXBW_VdqWdq = 0x30, 389 OP3_PMOVZXBD_VdqWdq = 0x31, 390 OP3_PMOVZXBQ_VdqWdq = 0x32, 391 OP3_PMOVZXWD_VdqWdq = 0x33, 392 OP3_PMOVZXWQ_VdqWdq = 0x34, 393 OP3_PMOVZXDQ_VdqWdq = 0x35, 394 OP3_PCMPGTQ_VdqWdq = 0x37, 395 OP3_PMINSB_VdqWdq = 0x38, 396 OP3_PMINSD_VdqWdq = 0x39, 397 OP3_PMINUW_VdqWdq = 0x3A, 398 OP3_PMINUD_VdqWdq = 0x3B, 399 OP3_PMAXSB_VdqWdq = 0x3C, 400 OP3_PMAXSD_VdqWdq = 0x3D, 401 OP3_PMAXUW_VdqWdq = 0x3E, 402 OP3_PMAXUD_VdqWdq = 0x3F, 403 OP3_PMULLD_VdqWdq = 0x40, 404 OP3_VBLENDVPS_VdqWdq = 0x4A, 405 OP3_VBLENDVPD_VdqWdq = 0x4B, 406 OP3_VPBLENDVB_VdqWdq = 0x4C, 407 OP3_VBROADCASTD_VxWx = 0x58, 408 OP3_VBROADCASTQ_VxWx = 0x59, 409 OP3_VBROADCASTB_VxWx = 0x78, 410 OP3_VBROADCASTW_VxWx = 0x79, 411 OP3_VFMADD231PS_VxHxWx = 0xB8, 412 OP3_VFMADD231PD_VxHxWx = 0xB8, 413 OP3_VFNMADD231PS_VxHxWx = 0xBC, 414 OP3_VFNMADD231PD_VxHxWx = 0xBC, 415 OP3_ANDN_GyByEy = 0xF2, 416 OP3_SHLX_GyEyBy = 0xF7, 417 OP3_SARX_GyEyBy = 0xF7, 418 OP3_SHRX_GyEyBy = 0xF7, 419 }; 420 421 // Test whether the given opcode should be printed with its operands reversed. 422 inline bool IsXMMReversedOperands(TwoByteOpcodeID opcode) { 423 switch (opcode) { 424 case OP2_MOVSD_WsdVsd: // also OP2_MOVPS_WpsVps 425 case OP2_MOVAPS_WsdVsd: 426 case OP2_MOVDQ_WdqVdq: 427 return true; 428 default: 429 break; 430 } 431 return false; 432 } 433 434 enum ThreeByteEscape { ESCAPE_38 = 0x38, ESCAPE_3A = 0x3A }; 435 436 enum VexOperandType { VEX_PS = 0, VEX_PD = 1, VEX_SS = 2, VEX_SD = 3 }; 437 438 inline OneByteOpcodeID jccRel8(Condition cond) { 439 return OneByteOpcodeID(OP_JCC_rel8 + std::underlying_type_t<Condition>(cond)); 440 } 441 inline TwoByteOpcodeID jccRel32(Condition cond) { 442 return TwoByteOpcodeID(OP2_JCC_rel32 + 443 std::underlying_type_t<Condition>(cond)); 444 } 445 inline TwoByteOpcodeID setccOpcode(Condition cond) { 446 return TwoByteOpcodeID(OP_SETCC + std::underlying_type_t<Condition>(cond)); 447 } 448 inline TwoByteOpcodeID cmovccOpcode(Condition cond) { 449 return TwoByteOpcodeID(OP2_CMOVCC_GvEv + 450 std::underlying_type_t<Condition>(cond)); 451 } 452 453 enum GroupOpcodeID { 454 GROUP1_OP_ADD = 0, 455 GROUP1_OP_OR = 1, 456 GROUP1_OP_ADC = 2, 457 GROUP1_OP_SBB = 3, 458 GROUP1_OP_AND = 4, 459 GROUP1_OP_SUB = 5, 460 GROUP1_OP_XOR = 6, 461 GROUP1_OP_CMP = 7, 462 463 GROUP1A_OP_POP = 0, 464 465 GROUP2_OP_ROL = 0, 466 GROUP2_OP_ROR = 1, 467 GROUP2_OP_SHL = 4, 468 GROUP2_OP_SHR = 5, 469 GROUP2_OP_SAR = 7, 470 471 GROUP3_OP_TEST = 0, 472 GROUP3_OP_NOT = 2, 473 GROUP3_OP_NEG = 3, 474 GROUP3_OP_MUL = 4, 475 GROUP3_OP_IMUL = 5, 476 GROUP3_OP_DIV = 6, 477 GROUP3_OP_IDIV = 7, 478 479 GROUP5_OP_INC = 0, 480 GROUP5_OP_DEC = 1, 481 GROUP5_OP_CALLN = 2, 482 GROUP5_OP_JMPN = 4, 483 GROUP5_OP_PUSH = 6, 484 485 FILD_OP_64 = 5, 486 487 FPU6_OP_FLD = 0, 488 FPU6_OP_FISTTP = 1, 489 FPU6_OP_FSTP = 3, 490 FPU6_OP_FLDCW = 5, 491 FPU6_OP_FISTP = 7, 492 493 GROUP11_MOV = 0 494 }; 495 496 static const RegisterID noBase = rbp; 497 static const RegisterID hasSib = rsp; 498 static const RegisterID noIndex = rsp; 499 #ifdef JS_CODEGEN_X64 500 static const RegisterID noBase2 = r13; 501 static const RegisterID hasSib2 = r12; 502 #endif 503 504 enum ModRmMode { 505 ModRmMemoryNoDisp, 506 ModRmMemoryDisp8, 507 ModRmMemoryDisp32, 508 ModRmRegister 509 }; 510 511 } // namespace X86Encoding 512 513 } // namespace jit 514 } // namespace js 515 516 #endif /* jit_x86_shared_Encoding_x86_shared_h */