extension-riscv-zicsr.h (2602B)
1 // Copyright 2022 the V8 project authors. All rights reserved. 2 // Use of this source code is governed by a BSD-style license that can be 3 // found in the LICENSE file. 4 5 #ifndef jit_riscv64_extension_Extension_riscv_zicsr_h_ 6 #define jit_riscv64_extension_Extension_riscv_zicsr_h_ 7 8 #include <stdint.h> 9 10 #include "jit/riscv64/extension/base-assembler-riscv.h" 11 #include "jit/riscv64/Register-riscv64.h" 12 namespace js { 13 namespace jit { 14 15 class AssemblerRISCVZicsr : public AssemblerRiscvBase { 16 public: 17 // CSR 18 void csrrw(Register rd, ControlStatusReg csr, Register rs1); 19 void csrrs(Register rd, ControlStatusReg csr, Register rs1); 20 void csrrc(Register rd, ControlStatusReg csr, Register rs1); 21 void csrrwi(Register rd, ControlStatusReg csr, uint8_t imm5); 22 void csrrsi(Register rd, ControlStatusReg csr, uint8_t imm5); 23 void csrrci(Register rd, ControlStatusReg csr, uint8_t imm5); 24 25 // illegal_trap 26 void illegal_trap(uint8_t code); 27 28 // Read instructions-retired counter 29 void rdinstret(Register rd) { csrrs(rd, csr_instret, zero_reg); } 30 void rdinstreth(Register rd) { csrrs(rd, csr_instreth, zero_reg); } 31 void rdcycle(Register rd) { csrrs(rd, csr_cycle, zero_reg); } 32 void rdcycleh(Register rd) { csrrs(rd, csr_cycleh, zero_reg); } 33 void rdtime(Register rd) { csrrs(rd, csr_time, zero_reg); } 34 void rdtimeh(Register rd) { csrrs(rd, csr_timeh, zero_reg); } 35 36 void csrr(Register rd, ControlStatusReg csr) { csrrs(rd, csr, zero_reg); } 37 void csrw(ControlStatusReg csr, Register rs) { csrrw(zero_reg, csr, rs); } 38 void csrs(ControlStatusReg csr, Register rs) { csrrs(zero_reg, csr, rs); } 39 void csrc(ControlStatusReg csr, Register rs) { csrrc(zero_reg, csr, rs); } 40 41 void csrwi(ControlStatusReg csr, uint8_t imm) { csrrwi(zero_reg, csr, imm); } 42 void csrsi(ControlStatusReg csr, uint8_t imm) { csrrsi(zero_reg, csr, imm); } 43 void csrci(ControlStatusReg csr, uint8_t imm) { csrrci(zero_reg, csr, imm); } 44 45 void frcsr(Register rd) { csrrs(rd, csr_fcsr, zero_reg); } 46 void fscsr(Register rd, Register rs) { csrrw(rd, csr_fcsr, rs); } 47 void fscsr(Register rs) { csrrw(zero_reg, csr_fcsr, rs); } 48 49 void frrm(Register rd) { csrrs(rd, csr_frm, zero_reg); } 50 void fsrm(Register rd, Register rs) { csrrw(rd, csr_frm, rs); } 51 void fsrm(Register rs) { csrrw(zero_reg, csr_frm, rs); } 52 53 void frflags(Register rd) { csrrs(rd, csr_fflags, zero_reg); } 54 void fsflags(Register rd, Register rs) { csrrw(rd, csr_fflags, rs); } 55 void fsflags(Register rs) { csrrw(zero_reg, csr_fflags, rs); } 56 }; 57 } // namespace jit 58 } // namespace js 59 #endif // jit_riscv64_extension_Extension_riscv_zicsr_h_