tor-browser

The Tor Browser
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extension-riscv-zicsr.cc (1520B)

      1 // Copyright 2022 the V8 project authors. All rights reserved.
      2 // Use of this source code is governed by a BSD-style license that can be
      3 // found in the LICENSE file.
      4 #include "jit/riscv64/extension/extension-riscv-zicsr.h"
      5 
      6 #include "jit/riscv64/constant/Constant-riscv64.h"
      7 #include "jit/riscv64/Register-riscv64.h"
      8 #include "jit/riscv64/Assembler-riscv64.h"
      9 #include "jit/riscv64/Architecture-riscv64.h"
     10 namespace js {
     11 namespace jit {
     12 
     13 void AssemblerRISCVZicsr::csrrw(Register rd, ControlStatusReg csr,
     14                                Register rs1) {
     15  GenInstrCSR_ir(0b001, rd, csr, rs1);
     16 }
     17 
     18 void AssemblerRISCVZicsr::csrrs(Register rd, ControlStatusReg csr,
     19                                Register rs1) {
     20  GenInstrCSR_ir(0b010, rd, csr, rs1);
     21 }
     22 
     23 void AssemblerRISCVZicsr::csrrc(Register rd, ControlStatusReg csr,
     24                                Register rs1) {
     25  GenInstrCSR_ir(0b011, rd, csr, rs1);
     26 }
     27 
     28 void AssemblerRISCVZicsr::csrrwi(Register rd, ControlStatusReg csr,
     29                                 uint8_t imm5) {
     30  GenInstrCSR_ii(0b101, rd, csr, imm5);
     31 }
     32 
     33 void AssemblerRISCVZicsr::csrrsi(Register rd, ControlStatusReg csr,
     34                                 uint8_t imm5) {
     35  GenInstrCSR_ii(0b110, rd, csr, imm5);
     36 }
     37 
     38 void AssemblerRISCVZicsr::csrrci(Register rd, ControlStatusReg csr,
     39                                 uint8_t imm5) {
     40  GenInstrCSR_ii(0b111, rd, csr, imm5);
     41 }
     42 
     43 void AssemblerRISCVZicsr::illegal_trap(uint8_t code) {
     44  csrrwi(zero, csr_cycle, code);
     45 }
     46 
     47 }  // namespace jit
     48 }  // namespace js