tor-browser

The Tor Browser
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extension-riscv-m.cc (2149B)

      1 // Copyright 2022 the V8 project authors. All rights reserved.
      2 // Use of this source code is governed by a BSD-style license that can be
      3 // found in the LICENSE file.
      4 #include "jit/riscv64/extension/extension-riscv-m.h"
      5 #include "jit/riscv64/Assembler-riscv64.h"
      6 #include "jit/riscv64/constant/Constant-riscv64.h"
      7 #include "jit/riscv64/Architecture-riscv64.h"
      8 namespace js {
      9 namespace jit {
     10 // RV32M Standard Extension
     11 
     12 void AssemblerRISCVM::mul(Register rd, Register rs1, Register rs2) {
     13  GenInstrALU_rr(0b0000001, 0b000, rd, rs1, rs2);
     14 }
     15 
     16 void AssemblerRISCVM::mulh(Register rd, Register rs1, Register rs2) {
     17  GenInstrALU_rr(0b0000001, 0b001, rd, rs1, rs2);
     18 }
     19 
     20 void AssemblerRISCVM::mulhsu(Register rd, Register rs1, Register rs2) {
     21  GenInstrALU_rr(0b0000001, 0b010, rd, rs1, rs2);
     22 }
     23 
     24 void AssemblerRISCVM::mulhu(Register rd, Register rs1, Register rs2) {
     25  GenInstrALU_rr(0b0000001, 0b011, rd, rs1, rs2);
     26 }
     27 
     28 void AssemblerRISCVM::div(Register rd, Register rs1, Register rs2) {
     29  GenInstrALU_rr(0b0000001, 0b100, rd, rs1, rs2);
     30 }
     31 
     32 void AssemblerRISCVM::divu(Register rd, Register rs1, Register rs2) {
     33  GenInstrALU_rr(0b0000001, 0b101, rd, rs1, rs2);
     34 }
     35 
     36 void AssemblerRISCVM::rem(Register rd, Register rs1, Register rs2) {
     37  GenInstrALU_rr(0b0000001, 0b110, rd, rs1, rs2);
     38 }
     39 
     40 void AssemblerRISCVM::remu(Register rd, Register rs1, Register rs2) {
     41  GenInstrALU_rr(0b0000001, 0b111, rd, rs1, rs2);
     42 }
     43 
     44 #ifdef JS_CODEGEN_RISCV64
     45 // RV64M Standard Extension (in addition to RV32M)
     46 
     47 void AssemblerRISCVM::mulw(Register rd, Register rs1, Register rs2) {
     48  GenInstrALUW_rr(0b0000001, 0b000, rd, rs1, rs2);
     49 }
     50 
     51 void AssemblerRISCVM::divw(Register rd, Register rs1, Register rs2) {
     52  GenInstrALUW_rr(0b0000001, 0b100, rd, rs1, rs2);
     53 }
     54 
     55 void AssemblerRISCVM::divuw(Register rd, Register rs1, Register rs2) {
     56  GenInstrALUW_rr(0b0000001, 0b101, rd, rs1, rs2);
     57 }
     58 
     59 void AssemblerRISCVM::remw(Register rd, Register rs1, Register rs2) {
     60  GenInstrALUW_rr(0b0000001, 0b110, rd, rs1, rs2);
     61 }
     62 
     63 void AssemblerRISCVM::remuw(Register rd, Register rs1, Register rs2) {
     64  GenInstrALUW_rr(0b0000001, 0b111, rd, rs1, rs2);
     65 }
     66 #endif
     67 }  // namespace jit
     68 }  // namespace js