extension-riscv-f.h (3280B)
1 // Copyright 2022 the V8 project authors. All rights reserved. 2 // Use of this source code is governed by a BSD-style license that can be 3 // found in the LICENSE file. 4 #ifndef jit_riscv64_extension_Extension_riscv_f_h_ 5 #define jit_riscv64_extension_Extension_riscv_f_h_ 6 7 #include <stdint.h> 8 9 #include "jit/riscv64/extension/base-assembler-riscv.h" 10 #include "jit/riscv64/Register-riscv64.h" 11 namespace js { 12 namespace jit { 13 class AssemblerRISCVF : public AssemblerRiscvBase { 14 // RV32F Standard Extension 15 public: 16 void flw(FPURegister rd, Register rs1, int16_t imm12); 17 void fsw(FPURegister source, Register base, int16_t imm12); 18 void fmadd_s(FPURegister rd, FPURegister rs1, FPURegister rs2, 19 FPURegister rs3, FPURoundingMode frm = RNE); 20 void fmsub_s(FPURegister rd, FPURegister rs1, FPURegister rs2, 21 FPURegister rs3, FPURoundingMode frm = RNE); 22 void fnmsub_s(FPURegister rd, FPURegister rs1, FPURegister rs2, 23 FPURegister rs3, FPURoundingMode frm = RNE); 24 void fnmadd_s(FPURegister rd, FPURegister rs1, FPURegister rs2, 25 FPURegister rs3, FPURoundingMode frm = RNE); 26 void fadd_s(FPURegister rd, FPURegister rs1, FPURegister rs2, 27 FPURoundingMode frm = RNE); 28 void fsub_s(FPURegister rd, FPURegister rs1, FPURegister rs2, 29 FPURoundingMode frm = RNE); 30 void fmul_s(FPURegister rd, FPURegister rs1, FPURegister rs2, 31 FPURoundingMode frm = RNE); 32 void fdiv_s(FPURegister rd, FPURegister rs1, FPURegister rs2, 33 FPURoundingMode frm = RNE); 34 void fsqrt_s(FPURegister rd, FPURegister rs1, FPURoundingMode frm = RNE); 35 void fsgnj_s(FPURegister rd, FPURegister rs1, FPURegister rs2); 36 void fsgnjn_s(FPURegister rd, FPURegister rs1, FPURegister rs2); 37 void fsgnjx_s(FPURegister rd, FPURegister rs1, FPURegister rs2); 38 void fmin_s(FPURegister rd, FPURegister rs1, FPURegister rs2); 39 void fmax_s(FPURegister rd, FPURegister rs1, FPURegister rs2); 40 void fcvt_w_s(Register rd, FPURegister rs1, FPURoundingMode frm = RNE); 41 void fcvt_wu_s(Register rd, FPURegister rs1, FPURoundingMode frm = RNE); 42 void fmv_x_w(Register rd, FPURegister rs1); 43 void feq_s(Register rd, FPURegister rs1, FPURegister rs2); 44 void flt_s(Register rd, FPURegister rs1, FPURegister rs2); 45 void fle_s(Register rd, FPURegister rs1, FPURegister rs2); 46 void fclass_s(Register rd, FPURegister rs1); 47 void fcvt_s_w(FPURegister rd, Register rs1, FPURoundingMode frm = RNE); 48 void fcvt_s_wu(FPURegister rd, Register rs1, FPURoundingMode frm = RNE); 49 void fmv_w_x(FPURegister rd, Register rs1); 50 51 #ifdef JS_CODEGEN_RISCV64 52 // RV64F Standard Extension (in addition to RV32F) 53 void fcvt_l_s(Register rd, FPURegister rs1, FPURoundingMode frm = RNE); 54 void fcvt_lu_s(Register rd, FPURegister rs1, FPURoundingMode frm = RNE); 55 void fcvt_s_l(FPURegister rd, Register rs1, FPURoundingMode frm = RNE); 56 void fcvt_s_lu(FPURegister rd, Register rs1, FPURoundingMode frm = RNE); 57 #endif 58 59 void fmv_s(FPURegister rd, FPURegister rs) { fsgnj_s(rd, rs, rs); } 60 void fabs_s(FPURegister rd, FPURegister rs) { fsgnjx_s(rd, rs, rs); } 61 void fneg_s(FPURegister rd, FPURegister rs) { fsgnjn_s(rd, rs, rs); } 62 }; 63 } // namespace jit 64 } // namespace js 65 #endif // jit_riscv64_extension_Extension_riscv_F_h_