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extension-riscv-f.cc (5487B)

      1 // Copyright 2022 the V8 project authors. All rights reserved.
      2 // Use of this source code is governed by a BSD-style license that can be
      3 // found in the LICENSE file.
      4 #include "jit/riscv64/extension/extension-riscv-f.h"
      5 #include "jit/riscv64/Assembler-riscv64.h"
      6 #include "jit/riscv64/constant/Constant-riscv64.h"
      7 #include "jit/riscv64/Architecture-riscv64.h"
      8 namespace js {
      9 namespace jit {
     10 
     11 // RV32F Standard Extension
     12 
     13 void AssemblerRISCVF::flw(FPURegister rd, Register rs1, int16_t imm12) {
     14  GenInstrLoadFP_ri(0b010, rd, rs1, imm12);
     15 }
     16 
     17 void AssemblerRISCVF::fsw(FPURegister source, Register base, int16_t imm12) {
     18  GenInstrStoreFP_rri(0b010, base, source, imm12);
     19 }
     20 
     21 void AssemblerRISCVF::fmadd_s(FPURegister rd, FPURegister rs1, FPURegister rs2,
     22                              FPURegister rs3, FPURoundingMode frm) {
     23  GenInstrR4(0b00, MADD, rd, rs1, rs2, rs3, frm);
     24 }
     25 
     26 void AssemblerRISCVF::fmsub_s(FPURegister rd, FPURegister rs1, FPURegister rs2,
     27                              FPURegister rs3, FPURoundingMode frm) {
     28  GenInstrR4(0b00, MSUB, rd, rs1, rs2, rs3, frm);
     29 }
     30 
     31 void AssemblerRISCVF::fnmsub_s(FPURegister rd, FPURegister rs1, FPURegister rs2,
     32                               FPURegister rs3, FPURoundingMode frm) {
     33  GenInstrR4(0b00, NMSUB, rd, rs1, rs2, rs3, frm);
     34 }
     35 
     36 void AssemblerRISCVF::fnmadd_s(FPURegister rd, FPURegister rs1, FPURegister rs2,
     37                               FPURegister rs3, FPURoundingMode frm) {
     38  GenInstrR4(0b00, NMADD, rd, rs1, rs2, rs3, frm);
     39 }
     40 
     41 void AssemblerRISCVF::fadd_s(FPURegister rd, FPURegister rs1, FPURegister rs2,
     42                             FPURoundingMode frm) {
     43  GenInstrALUFP_rr(0b0000000, frm, rd, rs1, rs2);
     44 }
     45 
     46 void AssemblerRISCVF::fsub_s(FPURegister rd, FPURegister rs1, FPURegister rs2,
     47                             FPURoundingMode frm) {
     48  GenInstrALUFP_rr(0b0000100, frm, rd, rs1, rs2);
     49 }
     50 
     51 void AssemblerRISCVF::fmul_s(FPURegister rd, FPURegister rs1, FPURegister rs2,
     52                             FPURoundingMode frm) {
     53  GenInstrALUFP_rr(0b0001000, frm, rd, rs1, rs2);
     54 }
     55 
     56 void AssemblerRISCVF::fdiv_s(FPURegister rd, FPURegister rs1, FPURegister rs2,
     57                             FPURoundingMode frm) {
     58  GenInstrALUFP_rr(0b0001100, frm, rd, rs1, rs2);
     59 }
     60 
     61 void AssemblerRISCVF::fsqrt_s(FPURegister rd, FPURegister rs1,
     62                              FPURoundingMode frm) {
     63  GenInstrALUFP_rr(0b0101100, frm, rd, rs1, zero_reg);
     64 }
     65 
     66 void AssemblerRISCVF::fsgnj_s(FPURegister rd, FPURegister rs1,
     67                              FPURegister rs2) {
     68  GenInstrALUFP_rr(0b0010000, 0b000, rd, rs1, rs2);
     69 }
     70 
     71 void AssemblerRISCVF::fsgnjn_s(FPURegister rd, FPURegister rs1,
     72                               FPURegister rs2) {
     73  GenInstrALUFP_rr(0b0010000, 0b001, rd, rs1, rs2);
     74 }
     75 
     76 void AssemblerRISCVF::fsgnjx_s(FPURegister rd, FPURegister rs1,
     77                               FPURegister rs2) {
     78  GenInstrALUFP_rr(0b0010000, 0b010, rd, rs1, rs2);
     79 }
     80 
     81 void AssemblerRISCVF::fmin_s(FPURegister rd, FPURegister rs1, FPURegister rs2) {
     82  GenInstrALUFP_rr(0b0010100, 0b000, rd, rs1, rs2);
     83 }
     84 
     85 void AssemblerRISCVF::fmax_s(FPURegister rd, FPURegister rs1, FPURegister rs2) {
     86  GenInstrALUFP_rr(0b0010100, 0b001, rd, rs1, rs2);
     87 }
     88 
     89 void AssemblerRISCVF::fcvt_w_s(Register rd, FPURegister rs1,
     90                               FPURoundingMode frm) {
     91  GenInstrALUFP_rr(0b1100000, frm, rd, rs1, zero_reg);
     92 }
     93 
     94 void AssemblerRISCVF::fcvt_wu_s(Register rd, FPURegister rs1,
     95                                FPURoundingMode frm) {
     96  GenInstrALUFP_rr(0b1100000, frm, rd, rs1, ToRegister(1));
     97 }
     98 
     99 void AssemblerRISCVF::fmv_x_w(Register rd, FPURegister rs1) {
    100  GenInstrALUFP_rr(0b1110000, 0b000, rd, rs1, zero_reg);
    101 }
    102 
    103 void AssemblerRISCVF::feq_s(Register rd, FPURegister rs1, FPURegister rs2) {
    104  GenInstrALUFP_rr(0b1010000, 0b010, rd, rs1, rs2);
    105 }
    106 
    107 void AssemblerRISCVF::flt_s(Register rd, FPURegister rs1, FPURegister rs2) {
    108  GenInstrALUFP_rr(0b1010000, 0b001, rd, rs1, rs2);
    109 }
    110 
    111 void AssemblerRISCVF::fle_s(Register rd, FPURegister rs1, FPURegister rs2) {
    112  GenInstrALUFP_rr(0b1010000, 0b000, rd, rs1, rs2);
    113 }
    114 
    115 void AssemblerRISCVF::fclass_s(Register rd, FPURegister rs1) {
    116  GenInstrALUFP_rr(0b1110000, 0b001, rd, rs1, zero_reg);
    117 }
    118 
    119 void AssemblerRISCVF::fcvt_s_w(FPURegister rd, Register rs1,
    120                               FPURoundingMode frm) {
    121  GenInstrALUFP_rr(0b1101000, frm, rd, rs1, zero_reg);
    122 }
    123 
    124 void AssemblerRISCVF::fcvt_s_wu(FPURegister rd, Register rs1,
    125                                FPURoundingMode frm) {
    126  GenInstrALUFP_rr(0b1101000, frm, rd, rs1, ToRegister(1));
    127 }
    128 
    129 void AssemblerRISCVF::fmv_w_x(FPURegister rd, Register rs1) {
    130  GenInstrALUFP_rr(0b1111000, 0b000, rd, rs1, zero_reg);
    131 }
    132 
    133 #ifdef JS_CODEGEN_RISCV64
    134 // RV64F Standard Extension (in addition to RV32F)
    135 
    136 void AssemblerRISCVF::fcvt_l_s(Register rd, FPURegister rs1,
    137                               FPURoundingMode frm) {
    138  GenInstrALUFP_rr(0b1100000, frm, rd, rs1, ToRegister(2));
    139 }
    140 
    141 void AssemblerRISCVF::fcvt_lu_s(Register rd, FPURegister rs1,
    142                                FPURoundingMode frm) {
    143  GenInstrALUFP_rr(0b1100000, frm, rd, rs1, ToRegister(3));
    144 }
    145 
    146 void AssemblerRISCVF::fcvt_s_l(FPURegister rd, Register rs1,
    147                               FPURoundingMode frm) {
    148  GenInstrALUFP_rr(0b1101000, frm, rd, rs1, ToRegister(2));
    149 }
    150 
    151 void AssemblerRISCVF::fcvt_s_lu(FPURegister rd, Register rs1,
    152                                FPURoundingMode frm) {
    153  GenInstrALUFP_rr(0b1101000, frm, rd, rs1, ToRegister(3));
    154 }
    155 #endif
    156 
    157 }  // namespace jit
    158 }  // namespace js