extension-riscv-d.h (3434B)
1 // Copyright 2022 the V8 project authors. All rights reserved. 2 // Use of this source code is governed by a BSD-style license that can be 3 // found in the LICENSE file. 4 #ifndef jit_riscv64_extension_Extension_riscv_d_h_ 5 #define jit_riscv64_extension_Extension_riscv_d_h_ 6 7 #include <stdint.h> 8 9 #include "jit/riscv64/extension/base-assembler-riscv.h" 10 #include "jit/riscv64/Register-riscv64.h" 11 namespace js { 12 namespace jit { 13 class AssemblerRISCVD : public AssemblerRiscvBase { 14 // RV32D Standard Extension 15 public: 16 void fld(FPURegister rd, Register rs1, int16_t imm12); 17 void fsd(FPURegister source, Register base, int16_t imm12); 18 void fmadd_d(FPURegister rd, FPURegister rs1, FPURegister rs2, 19 FPURegister rs3, FPURoundingMode frm = RNE); 20 void fmsub_d(FPURegister rd, FPURegister rs1, FPURegister rs2, 21 FPURegister rs3, FPURoundingMode frm = RNE); 22 void fnmsub_d(FPURegister rd, FPURegister rs1, FPURegister rs2, 23 FPURegister rs3, FPURoundingMode frm = RNE); 24 void fnmadd_d(FPURegister rd, FPURegister rs1, FPURegister rs2, 25 FPURegister rs3, FPURoundingMode frm = RNE); 26 void fadd_d(FPURegister rd, FPURegister rs1, FPURegister rs2, 27 FPURoundingMode frm = RNE); 28 void fsub_d(FPURegister rd, FPURegister rs1, FPURegister rs2, 29 FPURoundingMode frm = RNE); 30 void fmul_d(FPURegister rd, FPURegister rs1, FPURegister rs2, 31 FPURoundingMode frm = RNE); 32 void fdiv_d(FPURegister rd, FPURegister rs1, FPURegister rs2, 33 FPURoundingMode frm = RNE); 34 void fsqrt_d(FPURegister rd, FPURegister rs1, FPURoundingMode frm = RNE); 35 void fsgnj_d(FPURegister rd, FPURegister rs1, FPURegister rs2); 36 void fsgnjn_d(FPURegister rd, FPURegister rs1, FPURegister rs2); 37 void fsgnjx_d(FPURegister rd, FPURegister rs1, FPURegister rs2); 38 void fmin_d(FPURegister rd, FPURegister rs1, FPURegister rs2); 39 void fmax_d(FPURegister rd, FPURegister rs1, FPURegister rs2); 40 void fcvt_s_d(FPURegister rd, FPURegister rs1, FPURoundingMode frm = RNE); 41 void fcvt_d_s(FPURegister rd, FPURegister rs1, FPURoundingMode frm = RNE); 42 void feq_d(Register rd, FPURegister rs1, FPURegister rs2); 43 void flt_d(Register rd, FPURegister rs1, FPURegister rs2); 44 void fle_d(Register rd, FPURegister rs1, FPURegister rs2); 45 void fclass_d(Register rd, FPURegister rs1); 46 void fcvt_w_d(Register rd, FPURegister rs1, FPURoundingMode frm = RNE); 47 void fcvt_wu_d(Register rd, FPURegister rs1, FPURoundingMode frm = RNE); 48 void fcvt_d_w(FPURegister rd, Register rs1, FPURoundingMode frm = RNE); 49 void fcvt_d_wu(FPURegister rd, Register rs1, FPURoundingMode frm = RNE); 50 51 #ifdef JS_CODEGEN_RISCV64 52 // RV64D Standard Extension (in addition to RV32D) 53 void fcvt_l_d(Register rd, FPURegister rs1, FPURoundingMode frm = RNE); 54 void fcvt_lu_d(Register rd, FPURegister rs1, FPURoundingMode frm = RNE); 55 void fmv_x_d(Register rd, FPURegister rs1); 56 void fcvt_d_l(FPURegister rd, Register rs1, FPURoundingMode frm = RNE); 57 void fcvt_d_lu(FPURegister rd, Register rs1, FPURoundingMode frm = RNE); 58 void fmv_d_x(FPURegister rd, Register rs1); 59 #endif 60 61 void fmv_d(FPURegister rd, FPURegister rs) { fsgnj_d(rd, rs, rs); } 62 void fabs_d(FPURegister rd, FPURegister rs) { fsgnjx_d(rd, rs, rs); } 63 void fneg_d(FPURegister rd, FPURegister rs) { fsgnjn_d(rd, rs, rs); } 64 }; 65 } // namespace jit 66 } // namespace js 67 #endif // jit_riscv64_extension_Extension_riscv_D_h_