extension-riscv-d.cc (5843B)
1 // Copyright 2022 the V8 project authors. All rights reserved. 2 // Use of this source code is governed by a BSD-style license that can be 3 // found in the LICENSE file. 4 #include "jit/riscv64/extension/extension-riscv-d.h" 5 #include "jit/riscv64/Assembler-riscv64.h" 6 #include "jit/riscv64/constant/Constant-riscv64.h" 7 #include "jit/riscv64/Architecture-riscv64.h" 8 namespace js { 9 namespace jit { 10 // RV32D Standard Extension 11 12 void AssemblerRISCVD::fld(FPURegister rd, Register rs1, int16_t imm12) { 13 GenInstrLoadFP_ri(0b011, rd, rs1, imm12); 14 } 15 16 void AssemblerRISCVD::fsd(FPURegister source, Register base, int16_t imm12) { 17 GenInstrStoreFP_rri(0b011, base, source, imm12); 18 } 19 20 void AssemblerRISCVD::fmadd_d(FPURegister rd, FPURegister rs1, FPURegister rs2, 21 FPURegister rs3, FPURoundingMode frm) { 22 GenInstrR4(0b01, MADD, rd, rs1, rs2, rs3, frm); 23 } 24 25 void AssemblerRISCVD::fmsub_d(FPURegister rd, FPURegister rs1, FPURegister rs2, 26 FPURegister rs3, FPURoundingMode frm) { 27 GenInstrR4(0b01, MSUB, rd, rs1, rs2, rs3, frm); 28 } 29 30 void AssemblerRISCVD::fnmsub_d(FPURegister rd, FPURegister rs1, FPURegister rs2, 31 FPURegister rs3, FPURoundingMode frm) { 32 GenInstrR4(0b01, NMSUB, rd, rs1, rs2, rs3, frm); 33 } 34 35 void AssemblerRISCVD::fnmadd_d(FPURegister rd, FPURegister rs1, FPURegister rs2, 36 FPURegister rs3, FPURoundingMode frm) { 37 GenInstrR4(0b01, NMADD, rd, rs1, rs2, rs3, frm); 38 } 39 40 void AssemblerRISCVD::fadd_d(FPURegister rd, FPURegister rs1, FPURegister rs2, 41 FPURoundingMode frm) { 42 GenInstrALUFP_rr(0b0000001, frm, rd, rs1, rs2); 43 } 44 45 void AssemblerRISCVD::fsub_d(FPURegister rd, FPURegister rs1, FPURegister rs2, 46 FPURoundingMode frm) { 47 GenInstrALUFP_rr(0b0000101, frm, rd, rs1, rs2); 48 } 49 50 void AssemblerRISCVD::fmul_d(FPURegister rd, FPURegister rs1, FPURegister rs2, 51 FPURoundingMode frm) { 52 GenInstrALUFP_rr(0b0001001, frm, rd, rs1, rs2); 53 } 54 55 void AssemblerRISCVD::fdiv_d(FPURegister rd, FPURegister rs1, FPURegister rs2, 56 FPURoundingMode frm) { 57 GenInstrALUFP_rr(0b0001101, frm, rd, rs1, rs2); 58 } 59 60 void AssemblerRISCVD::fsqrt_d(FPURegister rd, FPURegister rs1, 61 FPURoundingMode frm) { 62 GenInstrALUFP_rr(0b0101101, frm, rd, rs1, zero_reg); 63 } 64 65 void AssemblerRISCVD::fsgnj_d(FPURegister rd, FPURegister rs1, 66 FPURegister rs2) { 67 GenInstrALUFP_rr(0b0010001, 0b000, rd, rs1, rs2); 68 } 69 70 void AssemblerRISCVD::fsgnjn_d(FPURegister rd, FPURegister rs1, 71 FPURegister rs2) { 72 GenInstrALUFP_rr(0b0010001, 0b001, rd, rs1, rs2); 73 } 74 75 void AssemblerRISCVD::fsgnjx_d(FPURegister rd, FPURegister rs1, 76 FPURegister rs2) { 77 GenInstrALUFP_rr(0b0010001, 0b010, rd, rs1, rs2); 78 } 79 80 void AssemblerRISCVD::fmin_d(FPURegister rd, FPURegister rs1, FPURegister rs2) { 81 GenInstrALUFP_rr(0b0010101, 0b000, rd, rs1, rs2); 82 } 83 84 void AssemblerRISCVD::fmax_d(FPURegister rd, FPURegister rs1, FPURegister rs2) { 85 GenInstrALUFP_rr(0b0010101, 0b001, rd, rs1, rs2); 86 } 87 88 void AssemblerRISCVD::fcvt_s_d(FPURegister rd, FPURegister rs1, 89 FPURoundingMode frm) { 90 GenInstrALUFP_rr(0b0100000, frm, rd, rs1, ToRegister(1)); 91 } 92 93 void AssemblerRISCVD::fcvt_d_s(FPURegister rd, FPURegister rs1, 94 FPURoundingMode frm) { 95 GenInstrALUFP_rr(0b0100001, frm, rd, rs1, zero_reg); 96 } 97 98 void AssemblerRISCVD::feq_d(Register rd, FPURegister rs1, FPURegister rs2) { 99 GenInstrALUFP_rr(0b1010001, 0b010, rd, rs1, rs2); 100 } 101 102 void AssemblerRISCVD::flt_d(Register rd, FPURegister rs1, FPURegister rs2) { 103 GenInstrALUFP_rr(0b1010001, 0b001, rd, rs1, rs2); 104 } 105 106 void AssemblerRISCVD::fle_d(Register rd, FPURegister rs1, FPURegister rs2) { 107 GenInstrALUFP_rr(0b1010001, 0b000, rd, rs1, rs2); 108 } 109 110 void AssemblerRISCVD::fclass_d(Register rd, FPURegister rs1) { 111 GenInstrALUFP_rr(0b1110001, 0b001, rd, rs1, zero_reg); 112 } 113 114 void AssemblerRISCVD::fcvt_w_d(Register rd, FPURegister rs1, 115 FPURoundingMode frm) { 116 GenInstrALUFP_rr(0b1100001, frm, rd, rs1, zero_reg); 117 } 118 119 void AssemblerRISCVD::fcvt_wu_d(Register rd, FPURegister rs1, 120 FPURoundingMode frm) { 121 GenInstrALUFP_rr(0b1100001, frm, rd, rs1, ToRegister(1)); 122 } 123 124 void AssemblerRISCVD::fcvt_d_w(FPURegister rd, Register rs1, 125 FPURoundingMode frm) { 126 GenInstrALUFP_rr(0b1101001, frm, rd, rs1, zero_reg); 127 } 128 129 void AssemblerRISCVD::fcvt_d_wu(FPURegister rd, Register rs1, 130 FPURoundingMode frm) { 131 GenInstrALUFP_rr(0b1101001, frm, rd, rs1, ToRegister(1)); 132 } 133 134 #ifdef JS_CODEGEN_RISCV64 135 // RV64D Standard Extension (in addition to RV32D) 136 137 void AssemblerRISCVD::fcvt_l_d(Register rd, FPURegister rs1, 138 FPURoundingMode frm) { 139 GenInstrALUFP_rr(0b1100001, frm, rd, rs1, ToRegister(2)); 140 } 141 142 void AssemblerRISCVD::fcvt_lu_d(Register rd, FPURegister rs1, 143 FPURoundingMode frm) { 144 GenInstrALUFP_rr(0b1100001, frm, rd, rs1, ToRegister(3)); 145 } 146 147 void AssemblerRISCVD::fmv_x_d(Register rd, FPURegister rs1) { 148 GenInstrALUFP_rr(0b1110001, 0b000, rd, rs1, zero_reg); 149 } 150 151 void AssemblerRISCVD::fcvt_d_l(FPURegister rd, Register rs1, 152 FPURoundingMode frm) { 153 GenInstrALUFP_rr(0b1101001, frm, rd, rs1, ToRegister(2)); 154 } 155 156 void AssemblerRISCVD::fcvt_d_lu(FPURegister rd, Register rs1, 157 FPURoundingMode frm) { 158 GenInstrALUFP_rr(0b1101001, frm, rd, rs1, ToRegister(3)); 159 } 160 161 void AssemblerRISCVD::fmv_d_x(FPURegister rd, Register rs1) { 162 GenInstrALUFP_rr(0b1111001, 0b000, rd, rs1, zero_reg); 163 } 164 #endif 165 166 } // namespace jit 167 } // namespace js