extension-riscv-c.h (2729B)
1 // Copyright 2022 the V8 project authors. All rights reserved. 2 // Use of this source code is governed by a BSD-style license that can be 3 // found in the LICENSE file. 4 #ifndef jit_riscv64_extension_Extension_riscv_c_h_ 5 #define jit_riscv64_extension_Extension_riscv_c_h_ 6 7 #include <stdint.h> 8 9 #include "jit/riscv64/extension/base-assembler-riscv.h" 10 #include "jit/riscv64/Register-riscv64.h" 11 namespace js { 12 namespace jit { 13 class AssemblerRISCVC : public AssemblerRiscvBase { 14 // RV64C Standard Extension 15 public: 16 void c_nop(); 17 void c_addi(Register rd, int8_t imm6); 18 19 void c_addi16sp(int16_t imm10); 20 void c_addi4spn(Register rd, int16_t uimm10); 21 void c_li(Register rd, int8_t imm6); 22 void c_lui(Register rd, int8_t imm6); 23 void c_slli(Register rd, uint8_t shamt6); 24 void c_lwsp(Register rd, uint16_t uimm8); 25 void c_jr(Register rs1); 26 void c_mv(Register rd, Register rs2); 27 void c_ebreak(); 28 void c_jalr(Register rs1); 29 void c_j(int16_t imm12); 30 void c_add(Register rd, Register rs2); 31 void c_sub(Register rd, Register rs2); 32 void c_and(Register rd, Register rs2); 33 void c_xor(Register rd, Register rs2); 34 void c_or(Register rd, Register rs2); 35 void c_swsp(Register rs2, uint16_t uimm8); 36 void c_lw(Register rd, Register rs1, uint16_t uimm7); 37 void c_sw(Register rs2, Register rs1, uint16_t uimm7); 38 void c_bnez(Register rs1, int16_t imm9); 39 void c_beqz(Register rs1, int16_t imm9); 40 void c_srli(Register rs1, int8_t shamt6); 41 void c_srai(Register rs1, int8_t shamt6); 42 void c_andi(Register rs1, int8_t imm6); 43 44 void c_fld(FPURegister rd, Register rs1, uint16_t uimm8); 45 void c_fsd(FPURegister rs2, Register rs1, uint16_t uimm8); 46 void c_fldsp(FPURegister rd, uint16_t uimm9); 47 void c_fsdsp(FPURegister rs2, uint16_t uimm9); 48 #ifdef JS_CODEGEN_RISCV64 49 void c_ld(Register rd, Register rs1, uint16_t uimm8); 50 void c_sd(Register rs2, Register rs1, uint16_t uimm8); 51 void c_subw(Register rd, Register rs2); 52 void c_addw(Register rd, Register rs2); 53 void c_addiw(Register rd, int8_t imm6); 54 void c_ldsp(Register rd, uint16_t uimm9); 55 void c_sdsp(Register rs2, uint16_t uimm9); 56 #endif 57 58 int CJumpOffset(Instr instr); 59 60 static bool IsCBranch(Instr instr); 61 static bool IsCJal(Instr instr); 62 63 inline int16_t cjumpOffset(Label* L) { 64 return (int16_t)branchOffsetHelper(L, OffsetSize::kOffset11); 65 } 66 inline int32_t cbranchOffset(Label* L) { 67 return branchOffsetHelper(L, OffsetSize::kOffset9); 68 } 69 70 void c_j(Label* L) { c_j(cjumpOffset(L)); } 71 void c_bnez(Register rs1, Label* L) { c_bnez(rs1, cbranchOffset(L)); } 72 void c_beqz(Register rs1, Label* L) { c_beqz(rs1, cbranchOffset(L)); } 73 }; 74 } // namespace jit 75 } // namespace js 76 #endif // jit_riscv64_extension_Extension_riscv_C_h_