extension-riscv-a.cc (4472B)
1 // Copyright 2022 the V8 project authors. All rights reserved. 2 // Use of this source code is governed by a BSD-style license that can be 3 // found in the LICENSE file. 4 #include "jit/riscv64/extension/extension-riscv-a.h" 5 #include "jit/riscv64/Assembler-riscv64.h" 6 #include "jit/riscv64/constant/Constant-riscv64.h" 7 #include "jit/riscv64/Architecture-riscv64.h" 8 namespace js { 9 namespace jit { 10 11 // RV32A Standard Extension 12 void AssemblerRISCVA::lr_w(bool aq, bool rl, Register rd, Register rs1) { 13 GenInstrRAtomic(0b00010, aq, rl, 0b010, rd, rs1, zero_reg); 14 } 15 16 void AssemblerRISCVA::sc_w(bool aq, bool rl, Register rd, Register rs1, 17 Register rs2) { 18 GenInstrRAtomic(0b00011, aq, rl, 0b010, rd, rs1, rs2); 19 } 20 21 void AssemblerRISCVA::amoswap_w(bool aq, bool rl, Register rd, Register rs1, 22 Register rs2) { 23 GenInstrRAtomic(0b00001, aq, rl, 0b010, rd, rs1, rs2); 24 } 25 26 void AssemblerRISCVA::amoadd_w(bool aq, bool rl, Register rd, Register rs1, 27 Register rs2) { 28 GenInstrRAtomic(0b00000, aq, rl, 0b010, rd, rs1, rs2); 29 } 30 31 void AssemblerRISCVA::amoxor_w(bool aq, bool rl, Register rd, Register rs1, 32 Register rs2) { 33 GenInstrRAtomic(0b00100, aq, rl, 0b010, rd, rs1, rs2); 34 } 35 36 void AssemblerRISCVA::amoand_w(bool aq, bool rl, Register rd, Register rs1, 37 Register rs2) { 38 GenInstrRAtomic(0b01100, aq, rl, 0b010, rd, rs1, rs2); 39 } 40 41 void AssemblerRISCVA::amoor_w(bool aq, bool rl, Register rd, Register rs1, 42 Register rs2) { 43 GenInstrRAtomic(0b01000, aq, rl, 0b010, rd, rs1, rs2); 44 } 45 46 void AssemblerRISCVA::amomin_w(bool aq, bool rl, Register rd, Register rs1, 47 Register rs2) { 48 GenInstrRAtomic(0b10000, aq, rl, 0b010, rd, rs1, rs2); 49 } 50 51 void AssemblerRISCVA::amomax_w(bool aq, bool rl, Register rd, Register rs1, 52 Register rs2) { 53 GenInstrRAtomic(0b10100, aq, rl, 0b010, rd, rs1, rs2); 54 } 55 56 void AssemblerRISCVA::amominu_w(bool aq, bool rl, Register rd, Register rs1, 57 Register rs2) { 58 GenInstrRAtomic(0b11000, aq, rl, 0b010, rd, rs1, rs2); 59 } 60 61 void AssemblerRISCVA::amomaxu_w(bool aq, bool rl, Register rd, Register rs1, 62 Register rs2) { 63 GenInstrRAtomic(0b11100, aq, rl, 0b010, rd, rs1, rs2); 64 } 65 66 // RV64A Standard Extension (in addition to RV32A) 67 #ifdef JS_CODEGEN_RISCV64 68 void AssemblerRISCVA::lr_d(bool aq, bool rl, Register rd, Register rs1) { 69 GenInstrRAtomic(0b00010, aq, rl, 0b011, rd, rs1, zero_reg); 70 } 71 72 void AssemblerRISCVA::sc_d(bool aq, bool rl, Register rd, Register rs1, 73 Register rs2) { 74 GenInstrRAtomic(0b00011, aq, rl, 0b011, rd, rs1, rs2); 75 } 76 77 void AssemblerRISCVA::amoswap_d(bool aq, bool rl, Register rd, Register rs1, 78 Register rs2) { 79 GenInstrRAtomic(0b00001, aq, rl, 0b011, rd, rs1, rs2); 80 } 81 82 void AssemblerRISCVA::amoadd_d(bool aq, bool rl, Register rd, Register rs1, 83 Register rs2) { 84 GenInstrRAtomic(0b00000, aq, rl, 0b011, rd, rs1, rs2); 85 } 86 87 void AssemblerRISCVA::amoxor_d(bool aq, bool rl, Register rd, Register rs1, 88 Register rs2) { 89 GenInstrRAtomic(0b00100, aq, rl, 0b011, rd, rs1, rs2); 90 } 91 92 void AssemblerRISCVA::amoand_d(bool aq, bool rl, Register rd, Register rs1, 93 Register rs2) { 94 GenInstrRAtomic(0b01100, aq, rl, 0b011, rd, rs1, rs2); 95 } 96 97 void AssemblerRISCVA::amoor_d(bool aq, bool rl, Register rd, Register rs1, 98 Register rs2) { 99 GenInstrRAtomic(0b01000, aq, rl, 0b011, rd, rs1, rs2); 100 } 101 102 void AssemblerRISCVA::amomin_d(bool aq, bool rl, Register rd, Register rs1, 103 Register rs2) { 104 GenInstrRAtomic(0b10000, aq, rl, 0b011, rd, rs1, rs2); 105 } 106 107 void AssemblerRISCVA::amomax_d(bool aq, bool rl, Register rd, Register rs1, 108 Register rs2) { 109 GenInstrRAtomic(0b10100, aq, rl, 0b011, rd, rs1, rs2); 110 } 111 112 void AssemblerRISCVA::amominu_d(bool aq, bool rl, Register rd, Register rs1, 113 Register rs2) { 114 GenInstrRAtomic(0b11000, aq, rl, 0b011, rd, rs1, rs2); 115 } 116 117 void AssemblerRISCVA::amomaxu_d(bool aq, bool rl, Register rd, Register rs1, 118 Register rs2) { 119 GenInstrRAtomic(0b11100, aq, rl, 0b011, rd, rs1, rs2); 120 } 121 #endif 122 } // namespace jit 123 } // namespace js