Constant-riscv-v.h (20732B)
1 // Copyright 2022 the V8 project authors. All rights reserved. 2 // Use of this source code is governed by a BSD-style license that can be 3 // found in the LICENSE file. 4 #ifndef jit_riscv64_constant_Constant_riscv64_v_h_ 5 #define jit_riscv64_constant_Constant_riscv64_v_h_ 6 #include "jit/riscv64/constant/Base-constant-riscv.h" 7 namespace js { 8 namespace jit { 9 10 namespace RVV { 11 enum TailAgnosticType { 12 ta = 0x1, // Tail agnostic 13 tu = 0x0, // Tail undisturbed 14 }; 15 16 enum MaskAgnosticType { 17 ma = 0x1, // Mask agnostic 18 mu = 0x0, // Mask undisturbed 19 }; 20 enum MaskType { 21 Mask = 0x0, // use the mask 22 NoMask = 0x1, 23 }; 24 } // namespace RVV 25 26 enum OpcodeRISCVV : uint32_t { 27 // RVV Extension 28 OP_IVV = OP_V | (0b000 << kFunct3Shift), 29 OP_FVV = OP_V | (0b001 << kFunct3Shift), 30 OP_MVV = OP_V | (0b010 << kFunct3Shift), 31 OP_IVI = OP_V | (0b011 << kFunct3Shift), 32 OP_IVX = OP_V | (0b100 << kFunct3Shift), 33 OP_FVF = OP_V | (0b101 << kFunct3Shift), 34 OP_MVX = OP_V | (0b110 << kFunct3Shift), 35 36 RO_V_VSETVLI = OP_V | (0b111 << kFunct3Shift) | 0b0 << 31, 37 RO_V_VSETIVLI = OP_V | (0b111 << kFunct3Shift) | 0b11 << 30, 38 RO_V_VSETVL = OP_V | (0b111 << kFunct3Shift) | 0b1 << 31, 39 40 // RVV LOAD/STORE 41 RO_V_VL = LOAD_FP | (0b00 << kRvvMopShift) | (0b000 << kRvvNfShift), 42 RO_V_VLS = LOAD_FP | (0b10 << kRvvMopShift) | (0b000 << kRvvNfShift), 43 RO_V_VLX = LOAD_FP | (0b11 << kRvvMopShift) | (0b000 << kRvvNfShift), 44 45 RO_V_VS = STORE_FP | (0b00 << kRvvMopShift) | (0b000 << kRvvNfShift), 46 RO_V_VSS = STORE_FP | (0b10 << kRvvMopShift) | (0b000 << kRvvNfShift), 47 RO_V_VSX = STORE_FP | (0b11 << kRvvMopShift) | (0b000 << kRvvNfShift), 48 RO_V_VSU = STORE_FP | (0b01 << kRvvMopShift) | (0b000 << kRvvNfShift), 49 // THE kFunct6Shift is mop 50 RO_V_VLSEG2 = LOAD_FP | (0b00 << kRvvMopShift) | (0b001 << kRvvNfShift), 51 RO_V_VLSEG3 = LOAD_FP | (0b00 << kRvvMopShift) | (0b010 << kRvvNfShift), 52 RO_V_VLSEG4 = LOAD_FP | (0b00 << kRvvMopShift) | (0b011 << kRvvNfShift), 53 RO_V_VLSEG5 = LOAD_FP | (0b00 << kRvvMopShift) | (0b100 << kRvvNfShift), 54 RO_V_VLSEG6 = LOAD_FP | (0b00 << kRvvMopShift) | (0b101 << kRvvNfShift), 55 RO_V_VLSEG7 = LOAD_FP | (0b00 << kRvvMopShift) | (0b110 << kRvvNfShift), 56 RO_V_VLSEG8 = LOAD_FP | (0b00 << kRvvMopShift) | (0b111 << kRvvNfShift), 57 58 RO_V_VSSEG2 = STORE_FP | (0b00 << kRvvMopShift) | (0b001 << kRvvNfShift), 59 RO_V_VSSEG3 = STORE_FP | (0b00 << kRvvMopShift) | (0b010 << kRvvNfShift), 60 RO_V_VSSEG4 = STORE_FP | (0b00 << kRvvMopShift) | (0b011 << kRvvNfShift), 61 RO_V_VSSEG5 = STORE_FP | (0b00 << kRvvMopShift) | (0b100 << kRvvNfShift), 62 RO_V_VSSEG6 = STORE_FP | (0b00 << kRvvMopShift) | (0b101 << kRvvNfShift), 63 RO_V_VSSEG7 = STORE_FP | (0b00 << kRvvMopShift) | (0b110 << kRvvNfShift), 64 RO_V_VSSEG8 = STORE_FP | (0b00 << kRvvMopShift) | (0b111 << kRvvNfShift), 65 66 RO_V_VLSSEG2 = LOAD_FP | (0b10 << kRvvMopShift) | (0b001 << kRvvNfShift), 67 RO_V_VLSSEG3 = LOAD_FP | (0b10 << kRvvMopShift) | (0b010 << kRvvNfShift), 68 RO_V_VLSSEG4 = LOAD_FP | (0b10 << kRvvMopShift) | (0b011 << kRvvNfShift), 69 RO_V_VLSSEG5 = LOAD_FP | (0b10 << kRvvMopShift) | (0b100 << kRvvNfShift), 70 RO_V_VLSSEG6 = LOAD_FP | (0b10 << kRvvMopShift) | (0b101 << kRvvNfShift), 71 RO_V_VLSSEG7 = LOAD_FP | (0b10 << kRvvMopShift) | (0b110 << kRvvNfShift), 72 RO_V_VLSSEG8 = LOAD_FP | (0b10 << kRvvMopShift) | (0b111 << kRvvNfShift), 73 74 RO_V_VSSSEG2 = STORE_FP | (0b10 << kRvvMopShift) | (0b001 << kRvvNfShift), 75 RO_V_VSSSEG3 = STORE_FP | (0b10 << kRvvMopShift) | (0b010 << kRvvNfShift), 76 RO_V_VSSSEG4 = STORE_FP | (0b10 << kRvvMopShift) | (0b011 << kRvvNfShift), 77 RO_V_VSSSEG5 = STORE_FP | (0b10 << kRvvMopShift) | (0b100 << kRvvNfShift), 78 RO_V_VSSSEG6 = STORE_FP | (0b10 << kRvvMopShift) | (0b101 << kRvvNfShift), 79 RO_V_VSSSEG7 = STORE_FP | (0b10 << kRvvMopShift) | (0b110 << kRvvNfShift), 80 RO_V_VSSSEG8 = STORE_FP | (0b10 << kRvvMopShift) | (0b111 << kRvvNfShift), 81 82 RO_V_VLXSEG2 = LOAD_FP | (0b11 << kRvvMopShift) | (0b001 << kRvvNfShift), 83 RO_V_VLXSEG3 = LOAD_FP | (0b11 << kRvvMopShift) | (0b010 << kRvvNfShift), 84 RO_V_VLXSEG4 = LOAD_FP | (0b11 << kRvvMopShift) | (0b011 << kRvvNfShift), 85 RO_V_VLXSEG5 = LOAD_FP | (0b11 << kRvvMopShift) | (0b100 << kRvvNfShift), 86 RO_V_VLXSEG6 = LOAD_FP | (0b11 << kRvvMopShift) | (0b101 << kRvvNfShift), 87 RO_V_VLXSEG7 = LOAD_FP | (0b11 << kRvvMopShift) | (0b110 << kRvvNfShift), 88 RO_V_VLXSEG8 = LOAD_FP | (0b11 << kRvvMopShift) | (0b111 << kRvvNfShift), 89 90 RO_V_VSXSEG2 = STORE_FP | (0b11 << kRvvMopShift) | (0b001 << kRvvNfShift), 91 RO_V_VSXSEG3 = STORE_FP | (0b11 << kRvvMopShift) | (0b010 << kRvvNfShift), 92 RO_V_VSXSEG4 = STORE_FP | (0b11 << kRvvMopShift) | (0b011 << kRvvNfShift), 93 RO_V_VSXSEG5 = STORE_FP | (0b11 << kRvvMopShift) | (0b100 << kRvvNfShift), 94 RO_V_VSXSEG6 = STORE_FP | (0b11 << kRvvMopShift) | (0b101 << kRvvNfShift), 95 RO_V_VSXSEG7 = STORE_FP | (0b11 << kRvvMopShift) | (0b110 << kRvvNfShift), 96 RO_V_VSXSEG8 = STORE_FP | (0b11 << kRvvMopShift) | (0b111 << kRvvNfShift), 97 98 // RVV Vector Arithmetic Instruction 99 VADD_FUNCT6 = 0b000000, 100 RO_V_VADD_VI = OP_IVI | (VADD_FUNCT6 << kRvvFunct6Shift), 101 RO_V_VADD_VV = OP_IVV | (VADD_FUNCT6 << kRvvFunct6Shift), 102 RO_V_VADD_VX = OP_IVX | (VADD_FUNCT6 << kRvvFunct6Shift), 103 104 VSUB_FUNCT6 = 0b000010, 105 RO_V_VSUB_VX = OP_IVX | (VSUB_FUNCT6 << kRvvFunct6Shift), 106 RO_V_VSUB_VV = OP_IVV | (VSUB_FUNCT6 << kRvvFunct6Shift), 107 108 VDIVU_FUNCT6 = 0b100000, 109 RO_V_VDIVU_VX = OP_MVX | (VDIVU_FUNCT6 << kRvvFunct6Shift), 110 RO_V_VDIVU_VV = OP_MVV | (VDIVU_FUNCT6 << kRvvFunct6Shift), 111 112 VDIV_FUNCT6 = 0b100001, 113 RO_V_VDIV_VX = OP_MVX | (VDIV_FUNCT6 << kRvvFunct6Shift), 114 RO_V_VDIV_VV = OP_MVV | (VDIV_FUNCT6 << kRvvFunct6Shift), 115 116 VREMU_FUNCT6 = 0b100010, 117 RO_V_VREMU_VX = OP_MVX | (VREMU_FUNCT6 << kRvvFunct6Shift), 118 RO_V_VREMU_VV = OP_MVV | (VREMU_FUNCT6 << kRvvFunct6Shift), 119 120 VREM_FUNCT6 = 0b100011, 121 RO_V_VREM_VX = OP_MVX | (VREM_FUNCT6 << kRvvFunct6Shift), 122 RO_V_VREM_VV = OP_MVV | (VREM_FUNCT6 << kRvvFunct6Shift), 123 124 VMULHU_FUNCT6 = 0b100100, 125 RO_V_VMULHU_VX = OP_MVX | (VMULHU_FUNCT6 << kRvvFunct6Shift), 126 RO_V_VMULHU_VV = OP_MVV | (VMULHU_FUNCT6 << kRvvFunct6Shift), 127 128 VMUL_FUNCT6 = 0b100101, 129 RO_V_VMUL_VX = OP_MVX | (VMUL_FUNCT6 << kRvvFunct6Shift), 130 RO_V_VMUL_VV = OP_MVV | (VMUL_FUNCT6 << kRvvFunct6Shift), 131 132 VWMUL_FUNCT6 = 0b111011, 133 RO_V_VWMUL_VX = OP_MVX | (VWMUL_FUNCT6 << kRvvFunct6Shift), 134 RO_V_VWMUL_VV = OP_MVV | (VWMUL_FUNCT6 << kRvvFunct6Shift), 135 136 VWMULU_FUNCT6 = 0b111000, 137 RO_V_VWMULU_VX = OP_MVX | (VWMULU_FUNCT6 << kRvvFunct6Shift), 138 RO_V_VWMULU_VV = OP_MVV | (VWMULU_FUNCT6 << kRvvFunct6Shift), 139 140 VMULHSU_FUNCT6 = 0b100110, 141 RO_V_VMULHSU_VX = OP_MVX | (VMULHSU_FUNCT6 << kRvvFunct6Shift), 142 RO_V_VMULHSU_VV = OP_MVV | (VMULHSU_FUNCT6 << kRvvFunct6Shift), 143 144 VMULH_FUNCT6 = 0b100111, 145 RO_V_VMULH_VX = OP_MVX | (VMULH_FUNCT6 << kRvvFunct6Shift), 146 RO_V_VMULH_VV = OP_MVV | (VMULH_FUNCT6 << kRvvFunct6Shift), 147 148 VWADD_FUNCT6 = 0b110001, 149 RO_V_VWADD_VV = OP_MVV | (VWADD_FUNCT6 << kRvvFunct6Shift), 150 RO_V_VWADD_VX = OP_MVX | (VWADD_FUNCT6 << kRvvFunct6Shift), 151 152 VWADDU_FUNCT6 = 0b110000, 153 RO_V_VWADDU_VV = OP_MVV | (VWADDU_FUNCT6 << kRvvFunct6Shift), 154 RO_V_VWADDU_VX = OP_MVX | (VWADDU_FUNCT6 << kRvvFunct6Shift), 155 156 VWADDUW_FUNCT6 = 0b110101, 157 RO_V_VWADDUW_VX = OP_MVX | (VWADDUW_FUNCT6 << kRvvFunct6Shift), 158 RO_V_VWADDUW_VV = OP_MVV | (VWADDUW_FUNCT6 << kRvvFunct6Shift), 159 160 VCOMPRESS_FUNCT6 = 0b010111, 161 RO_V_VCOMPRESS_VV = OP_MVV | (VCOMPRESS_FUNCT6 << kRvvFunct6Shift), 162 163 VSADDU_FUNCT6 = 0b100000, 164 RO_V_VSADDU_VI = OP_IVI | (VSADDU_FUNCT6 << kRvvFunct6Shift), 165 RO_V_VSADDU_VV = OP_IVV | (VSADDU_FUNCT6 << kRvvFunct6Shift), 166 RO_V_VSADDU_VX = OP_IVX | (VSADDU_FUNCT6 << kRvvFunct6Shift), 167 168 VSADD_FUNCT6 = 0b100001, 169 RO_V_VSADD_VI = OP_IVI | (VSADD_FUNCT6 << kRvvFunct6Shift), 170 RO_V_VSADD_VV = OP_IVV | (VSADD_FUNCT6 << kRvvFunct6Shift), 171 RO_V_VSADD_VX = OP_IVX | (VSADD_FUNCT6 << kRvvFunct6Shift), 172 173 VSSUB_FUNCT6 = 0b100011, 174 RO_V_VSSUB_VV = OP_IVV | (VSSUB_FUNCT6 << kRvvFunct6Shift), 175 RO_V_VSSUB_VX = OP_IVX | (VSSUB_FUNCT6 << kRvvFunct6Shift), 176 177 VSSUBU_FUNCT6 = 0b100010, 178 RO_V_VSSUBU_VV = OP_IVV | (VSSUBU_FUNCT6 << kRvvFunct6Shift), 179 RO_V_VSSUBU_VX = OP_IVX | (VSSUBU_FUNCT6 << kRvvFunct6Shift), 180 181 VRSUB_FUNCT6 = 0b000011, 182 RO_V_VRSUB_VX = OP_IVX | (VRSUB_FUNCT6 << kRvvFunct6Shift), 183 RO_V_VRSUB_VI = OP_IVI | (VRSUB_FUNCT6 << kRvvFunct6Shift), 184 185 VMINU_FUNCT6 = 0b000100, 186 RO_V_VMINU_VX = OP_IVX | (VMINU_FUNCT6 << kRvvFunct6Shift), 187 RO_V_VMINU_VV = OP_IVV | (VMINU_FUNCT6 << kRvvFunct6Shift), 188 189 VMIN_FUNCT6 = 0b000101, 190 RO_V_VMIN_VX = OP_IVX | (VMIN_FUNCT6 << kRvvFunct6Shift), 191 RO_V_VMIN_VV = OP_IVV | (VMIN_FUNCT6 << kRvvFunct6Shift), 192 193 VMAXU_FUNCT6 = 0b000110, 194 RO_V_VMAXU_VX = OP_IVX | (VMAXU_FUNCT6 << kRvvFunct6Shift), 195 RO_V_VMAXU_VV = OP_IVV | (VMAXU_FUNCT6 << kRvvFunct6Shift), 196 197 VMAX_FUNCT6 = 0b000111, 198 RO_V_VMAX_VX = OP_IVX | (VMAX_FUNCT6 << kRvvFunct6Shift), 199 RO_V_VMAX_VV = OP_IVV | (VMAX_FUNCT6 << kRvvFunct6Shift), 200 201 VAND_FUNCT6 = 0b001001, 202 RO_V_VAND_VI = OP_IVI | (VAND_FUNCT6 << kRvvFunct6Shift), 203 RO_V_VAND_VV = OP_IVV | (VAND_FUNCT6 << kRvvFunct6Shift), 204 RO_V_VAND_VX = OP_IVX | (VAND_FUNCT6 << kRvvFunct6Shift), 205 206 VOR_FUNCT6 = 0b001010, 207 RO_V_VOR_VI = OP_IVI | (VOR_FUNCT6 << kRvvFunct6Shift), 208 RO_V_VOR_VV = OP_IVV | (VOR_FUNCT6 << kRvvFunct6Shift), 209 RO_V_VOR_VX = OP_IVX | (VOR_FUNCT6 << kRvvFunct6Shift), 210 211 VXOR_FUNCT6 = 0b001011, 212 RO_V_VXOR_VI = OP_IVI | (VXOR_FUNCT6 << kRvvFunct6Shift), 213 RO_V_VXOR_VV = OP_IVV | (VXOR_FUNCT6 << kRvvFunct6Shift), 214 RO_V_VXOR_VX = OP_IVX | (VXOR_FUNCT6 << kRvvFunct6Shift), 215 216 VRGATHER_FUNCT6 = 0b001100, 217 RO_V_VRGATHER_VI = OP_IVI | (VRGATHER_FUNCT6 << kRvvFunct6Shift), 218 RO_V_VRGATHER_VV = OP_IVV | (VRGATHER_FUNCT6 << kRvvFunct6Shift), 219 RO_V_VRGATHER_VX = OP_IVX | (VRGATHER_FUNCT6 << kRvvFunct6Shift), 220 221 VMV_FUNCT6 = 0b010111, 222 RO_V_VMV_VI = OP_IVI | (VMV_FUNCT6 << kRvvFunct6Shift), 223 RO_V_VMV_VV = OP_IVV | (VMV_FUNCT6 << kRvvFunct6Shift), 224 RO_V_VMV_VX = OP_IVX | (VMV_FUNCT6 << kRvvFunct6Shift), 225 RO_V_VFMV_VF = OP_FVF | (VMV_FUNCT6 << kRvvFunct6Shift), 226 227 RO_V_VMERGE_VI = RO_V_VMV_VI, 228 RO_V_VMERGE_VV = RO_V_VMV_VV, 229 RO_V_VMERGE_VX = RO_V_VMV_VX, 230 231 VMSEQ_FUNCT6 = 0b011000, 232 RO_V_VMSEQ_VI = OP_IVI | (VMSEQ_FUNCT6 << kRvvFunct6Shift), 233 RO_V_VMSEQ_VV = OP_IVV | (VMSEQ_FUNCT6 << kRvvFunct6Shift), 234 RO_V_VMSEQ_VX = OP_IVX | (VMSEQ_FUNCT6 << kRvvFunct6Shift), 235 236 VMSNE_FUNCT6 = 0b011001, 237 RO_V_VMSNE_VI = OP_IVI | (VMSNE_FUNCT6 << kRvvFunct6Shift), 238 RO_V_VMSNE_VV = OP_IVV | (VMSNE_FUNCT6 << kRvvFunct6Shift), 239 RO_V_VMSNE_VX = OP_IVX | (VMSNE_FUNCT6 << kRvvFunct6Shift), 240 241 VMSLTU_FUNCT6 = 0b011010, 242 RO_V_VMSLTU_VV = OP_IVV | (VMSLTU_FUNCT6 << kRvvFunct6Shift), 243 RO_V_VMSLTU_VX = OP_IVX | (VMSLTU_FUNCT6 << kRvvFunct6Shift), 244 245 VMSLT_FUNCT6 = 0b011011, 246 RO_V_VMSLT_VV = OP_IVV | (VMSLT_FUNCT6 << kRvvFunct6Shift), 247 RO_V_VMSLT_VX = OP_IVX | (VMSLT_FUNCT6 << kRvvFunct6Shift), 248 249 VMSLE_FUNCT6 = 0b011101, 250 RO_V_VMSLE_VI = OP_IVI | (VMSLE_FUNCT6 << kRvvFunct6Shift), 251 RO_V_VMSLE_VV = OP_IVV | (VMSLE_FUNCT6 << kRvvFunct6Shift), 252 RO_V_VMSLE_VX = OP_IVX | (VMSLE_FUNCT6 << kRvvFunct6Shift), 253 254 VMSLEU_FUNCT6 = 0b011100, 255 RO_V_VMSLEU_VI = OP_IVI | (VMSLEU_FUNCT6 << kRvvFunct6Shift), 256 RO_V_VMSLEU_VV = OP_IVV | (VMSLEU_FUNCT6 << kRvvFunct6Shift), 257 RO_V_VMSLEU_VX = OP_IVX | (VMSLEU_FUNCT6 << kRvvFunct6Shift), 258 259 VMSGTU_FUNCT6 = 0b011110, 260 RO_V_VMSGTU_VI = OP_IVI | (VMSGTU_FUNCT6 << kRvvFunct6Shift), 261 RO_V_VMSGTU_VX = OP_IVX | (VMSGTU_FUNCT6 << kRvvFunct6Shift), 262 263 VMSGT_FUNCT6 = 0b011111, 264 RO_V_VMSGT_VI = OP_IVI | (VMSGT_FUNCT6 << kRvvFunct6Shift), 265 RO_V_VMSGT_VX = OP_IVX | (VMSGT_FUNCT6 << kRvvFunct6Shift), 266 267 VSLIDEUP_FUNCT6 = 0b001110, 268 RO_V_VSLIDEUP_VI = OP_IVI | (VSLIDEUP_FUNCT6 << kRvvFunct6Shift), 269 RO_V_VSLIDEUP_VX = OP_IVX | (VSLIDEUP_FUNCT6 << kRvvFunct6Shift), 270 271 VSLIDEDOWN_FUNCT6 = 0b001111, 272 RO_V_VSLIDEDOWN_VI = OP_IVI | (VSLIDEDOWN_FUNCT6 << kRvvFunct6Shift), 273 RO_V_VSLIDEDOWN_VX = OP_IVX | (VSLIDEDOWN_FUNCT6 << kRvvFunct6Shift), 274 275 VSRL_FUNCT6 = 0b101000, 276 RO_V_VSRL_VI = OP_IVI | (VSRL_FUNCT6 << kRvvFunct6Shift), 277 RO_V_VSRL_VV = OP_IVV | (VSRL_FUNCT6 << kRvvFunct6Shift), 278 RO_V_VSRL_VX = OP_IVX | (VSRL_FUNCT6 << kRvvFunct6Shift), 279 280 VSRA_FUNCT6 = 0b101001, 281 RO_V_VSRA_VI = OP_IVI | (VSRA_FUNCT6 << kRvvFunct6Shift), 282 RO_V_VSRA_VV = OP_IVV | (VSRA_FUNCT6 << kRvvFunct6Shift), 283 RO_V_VSRA_VX = OP_IVX | (VSRA_FUNCT6 << kRvvFunct6Shift), 284 285 VSLL_FUNCT6 = 0b100101, 286 RO_V_VSLL_VI = OP_IVI | (VSLL_FUNCT6 << kRvvFunct6Shift), 287 RO_V_VSLL_VV = OP_IVV | (VSLL_FUNCT6 << kRvvFunct6Shift), 288 RO_V_VSLL_VX = OP_IVX | (VSLL_FUNCT6 << kRvvFunct6Shift), 289 290 VSMUL_FUNCT6 = 0b100111, 291 RO_V_VSMUL_VV = OP_IVV | (VSMUL_FUNCT6 << kRvvFunct6Shift), 292 RO_V_VSMUL_VX = OP_IVX | (VSMUL_FUNCT6 << kRvvFunct6Shift), 293 294 VADC_FUNCT6 = 0b010000, 295 RO_V_VADC_VI = OP_IVI | (VADC_FUNCT6 << kRvvFunct6Shift), 296 RO_V_VADC_VV = OP_IVV | (VADC_FUNCT6 << kRvvFunct6Shift), 297 RO_V_VADC_VX = OP_IVX | (VADC_FUNCT6 << kRvvFunct6Shift), 298 299 VMADC_FUNCT6 = 0b010001, 300 RO_V_VMADC_VI = OP_IVI | (VMADC_FUNCT6 << kRvvFunct6Shift), 301 RO_V_VMADC_VV = OP_IVV | (VMADC_FUNCT6 << kRvvFunct6Shift), 302 RO_V_VMADC_VX = OP_IVX | (VMADC_FUNCT6 << kRvvFunct6Shift), 303 304 VWXUNARY0_FUNCT6 = 0b010000, 305 VRXUNARY0_FUNCT6 = 0b010000, 306 VMUNARY0_FUNCT6 = 0b010100, 307 308 RO_V_VWXUNARY0 = OP_MVV | (VWXUNARY0_FUNCT6 << kRvvFunct6Shift), 309 RO_V_VRXUNARY0 = OP_MVX | (VRXUNARY0_FUNCT6 << kRvvFunct6Shift), 310 RO_V_VMUNARY0 = OP_MVV | (VMUNARY0_FUNCT6 << kRvvFunct6Shift), 311 312 VID_V = 0b10001, 313 314 VXUNARY0_FUNCT6 = 0b010010, 315 RO_V_VXUNARY0 = OP_MVV | (VXUNARY0_FUNCT6 << kRvvFunct6Shift), 316 317 VWFUNARY0_FUNCT6 = 0b010000, 318 RO_V_VFMV_FS = OP_FVV | (VWFUNARY0_FUNCT6 << kRvvFunct6Shift), 319 320 VRFUNARY0_FUNCT6 = 0b010000, 321 RO_V_VFMV_SF = OP_FVF | (VRFUNARY0_FUNCT6 << kRvvFunct6Shift), 322 323 VREDMAXU_FUNCT6 = 0b000110, 324 RO_V_VREDMAXU = OP_MVV | (VREDMAXU_FUNCT6 << kRvvFunct6Shift), 325 VREDMAX_FUNCT6 = 0b000111, 326 RO_V_VREDMAX = OP_MVV | (VREDMAX_FUNCT6 << kRvvFunct6Shift), 327 328 VREDMINU_FUNCT6 = 0b000100, 329 RO_V_VREDMINU = OP_MVV | (VREDMINU_FUNCT6 << kRvvFunct6Shift), 330 VREDMIN_FUNCT6 = 0b000101, 331 RO_V_VREDMIN = OP_MVV | (VREDMIN_FUNCT6 << kRvvFunct6Shift), 332 333 VFUNARY0_FUNCT6 = 0b010010, 334 RO_V_VFUNARY0 = OP_FVV | (VFUNARY0_FUNCT6 << kRvvFunct6Shift), 335 VFUNARY1_FUNCT6 = 0b010011, 336 RO_V_VFUNARY1 = OP_FVV | (VFUNARY1_FUNCT6 << kRvvFunct6Shift), 337 338 VFCVT_XU_F_V = 0b00000, 339 VFCVT_X_F_V = 0b00001, 340 VFCVT_F_XU_V = 0b00010, 341 VFCVT_F_X_V = 0b00011, 342 VFWCVT_XU_F_V = 0b01000, 343 VFWCVT_X_F_V = 0b01001, 344 VFWCVT_F_XU_V = 0b01010, 345 VFWCVT_F_X_V = 0b01011, 346 VFWCVT_F_F_V = 0b01100, 347 VFNCVT_F_F_W = 0b10100, 348 VFNCVT_X_F_W = 0b10001, 349 VFNCVT_XU_F_W = 0b10000, 350 351 VFCLASS_V = 0b10000, 352 VFSQRT_V = 0b00000, 353 VFRSQRT7_V = 0b00100, 354 VFREC7_V = 0b00101, 355 356 VFADD_FUNCT6 = 0b000000, 357 RO_V_VFADD_VV = OP_FVV | (VFADD_FUNCT6 << kRvvFunct6Shift), 358 RO_V_VFADD_VF = OP_FVF | (VFADD_FUNCT6 << kRvvFunct6Shift), 359 360 VFSUB_FUNCT6 = 0b000010, 361 RO_V_VFSUB_VV = OP_FVV | (VFSUB_FUNCT6 << kRvvFunct6Shift), 362 RO_V_VFSUB_VF = OP_FVF | (VFSUB_FUNCT6 << kRvvFunct6Shift), 363 364 VFDIV_FUNCT6 = 0b100000, 365 RO_V_VFDIV_VV = OP_FVV | (VFDIV_FUNCT6 << kRvvFunct6Shift), 366 RO_V_VFDIV_VF = OP_FVF | (VFDIV_FUNCT6 << kRvvFunct6Shift), 367 368 VFMUL_FUNCT6 = 0b100100, 369 RO_V_VFMUL_VV = OP_FVV | (VFMUL_FUNCT6 << kRvvFunct6Shift), 370 RO_V_VFMUL_VF = OP_FVF | (VFMUL_FUNCT6 << kRvvFunct6Shift), 371 372 // Vector Widening Floating-Point Add/Subtract Instructions 373 VFWADD_FUNCT6 = 0b110000, 374 RO_V_VFWADD_VV = OP_FVV | (VFWADD_FUNCT6 << kRvvFunct6Shift), 375 RO_V_VFWADD_VF = OP_FVF | (VFWADD_FUNCT6 << kRvvFunct6Shift), 376 377 VFWSUB_FUNCT6 = 0b110010, 378 RO_V_VFWSUB_VV = OP_FVV | (VFWSUB_FUNCT6 << kRvvFunct6Shift), 379 RO_V_VFWSUB_VF = OP_FVF | (VFWSUB_FUNCT6 << kRvvFunct6Shift), 380 381 VFWADD_W_FUNCT6 = 0b110100, 382 RO_V_VFWADD_W_VV = OP_FVV | (VFWADD_W_FUNCT6 << kRvvFunct6Shift), 383 RO_V_VFWADD_W_VF = OP_FVF | (VFWADD_W_FUNCT6 << kRvvFunct6Shift), 384 385 VFWSUB_W_FUNCT6 = 0b110110, 386 RO_V_VFWSUB_W_VV = OP_FVV | (VFWSUB_W_FUNCT6 << kRvvFunct6Shift), 387 RO_V_VFWSUB_W_VF = OP_FVF | (VFWSUB_W_FUNCT6 << kRvvFunct6Shift), 388 389 // Vector Widening Floating-Point Reduction Instructions 390 VFWREDUSUM_FUNCT6 = 0b110001, 391 RO_V_VFWREDUSUM_VV = OP_FVV | (VFWREDUSUM_FUNCT6 << kRvvFunct6Shift), 392 393 VFWREDOSUM_FUNCT6 = 0b110011, 394 RO_V_VFWREDOSUM_VV = OP_FVV | (VFWREDOSUM_FUNCT6 << kRvvFunct6Shift), 395 396 // Vector Widening Floating-Point Multiply 397 VFWMUL_FUNCT6 = 0b111000, 398 RO_V_VFWMUL_VV = OP_FVV | (VFWMUL_FUNCT6 << kRvvFunct6Shift), 399 RO_V_VFWMUL_VF = OP_FVF | (VFWMUL_FUNCT6 << kRvvFunct6Shift), 400 401 VMFEQ_FUNCT6 = 0b011000, 402 RO_V_VMFEQ_VV = OP_FVV | (VMFEQ_FUNCT6 << kRvvFunct6Shift), 403 RO_V_VMFEQ_VF = OP_FVF | (VMFEQ_FUNCT6 << kRvvFunct6Shift), 404 405 VMFNE_FUNCT6 = 0b011100, 406 RO_V_VMFNE_VV = OP_FVV | (VMFNE_FUNCT6 << kRvvFunct6Shift), 407 RO_V_VMFNE_VF = OP_FVF | (VMFNE_FUNCT6 << kRvvFunct6Shift), 408 409 VMFLT_FUNCT6 = 0b011011, 410 RO_V_VMFLT_VV = OP_FVV | (VMFLT_FUNCT6 << kRvvFunct6Shift), 411 RO_V_VMFLT_VF = OP_FVF | (VMFLT_FUNCT6 << kRvvFunct6Shift), 412 413 VMFLE_FUNCT6 = 0b011001, 414 RO_V_VMFLE_VV = OP_FVV | (VMFLE_FUNCT6 << kRvvFunct6Shift), 415 RO_V_VMFLE_VF = OP_FVF | (VMFLE_FUNCT6 << kRvvFunct6Shift), 416 417 VMFGE_FUNCT6 = 0b011111, 418 RO_V_VMFGE_VF = OP_FVF | (VMFGE_FUNCT6 << kRvvFunct6Shift), 419 420 VMFGT_FUNCT6 = 0b011101, 421 RO_V_VMFGT_VF = OP_FVF | (VMFGT_FUNCT6 << kRvvFunct6Shift), 422 423 VFMAX_FUNCT6 = 0b000110, 424 RO_V_VFMAX_VV = OP_FVV | (VFMAX_FUNCT6 << kRvvFunct6Shift), 425 RO_V_VFMAX_VF = OP_FVF | (VFMAX_FUNCT6 << kRvvFunct6Shift), 426 427 VFREDMAX_FUNCT6 = 0b0001111, 428 RO_V_VFREDMAX_VV = OP_FVV | (VFREDMAX_FUNCT6 << kRvvFunct6Shift), 429 430 VFMIN_FUNCT6 = 0b000100, 431 RO_V_VFMIN_VV = OP_FVV | (VFMIN_FUNCT6 << kRvvFunct6Shift), 432 RO_V_VFMIN_VF = OP_FVF | (VFMIN_FUNCT6 << kRvvFunct6Shift), 433 434 VFSGNJ_FUNCT6 = 0b001000, 435 RO_V_VFSGNJ_VV = OP_FVV | (VFSGNJ_FUNCT6 << kRvvFunct6Shift), 436 RO_V_VFSGNJ_VF = OP_FVF | (VFSGNJ_FUNCT6 << kRvvFunct6Shift), 437 438 VFSGNJN_FUNCT6 = 0b001001, 439 RO_V_VFSGNJN_VV = OP_FVV | (VFSGNJN_FUNCT6 << kRvvFunct6Shift), 440 RO_V_VFSGNJN_VF = OP_FVF | (VFSGNJN_FUNCT6 << kRvvFunct6Shift), 441 442 VFSGNJX_FUNCT6 = 0b001010, 443 RO_V_VFSGNJX_VV = OP_FVV | (VFSGNJX_FUNCT6 << kRvvFunct6Shift), 444 RO_V_VFSGNJX_VF = OP_FVF | (VFSGNJX_FUNCT6 << kRvvFunct6Shift), 445 446 VFMADD_FUNCT6 = 0b101000, 447 RO_V_VFMADD_VV = OP_FVV | (VFMADD_FUNCT6 << kRvvFunct6Shift), 448 RO_V_VFMADD_VF = OP_FVF | (VFMADD_FUNCT6 << kRvvFunct6Shift), 449 450 VFNMADD_FUNCT6 = 0b101001, 451 RO_V_VFNMADD_VV = OP_FVV | (VFNMADD_FUNCT6 << kRvvFunct6Shift), 452 RO_V_VFNMADD_VF = OP_FVF | (VFNMADD_FUNCT6 << kRvvFunct6Shift), 453 454 VFMSUB_FUNCT6 = 0b101010, 455 RO_V_VFMSUB_VV = OP_FVV | (VFMSUB_FUNCT6 << kRvvFunct6Shift), 456 RO_V_VFMSUB_VF = OP_FVF | (VFMSUB_FUNCT6 << kRvvFunct6Shift), 457 458 VFNMSUB_FUNCT6 = 0b101011, 459 RO_V_VFNMSUB_VV = OP_FVV | (VFNMSUB_FUNCT6 << kRvvFunct6Shift), 460 RO_V_VFNMSUB_VF = OP_FVF | (VFNMSUB_FUNCT6 << kRvvFunct6Shift), 461 462 VFMACC_FUNCT6 = 0b101100, 463 RO_V_VFMACC_VV = OP_FVV | (VFMACC_FUNCT6 << kRvvFunct6Shift), 464 RO_V_VFMACC_VF = OP_FVF | (VFMACC_FUNCT6 << kRvvFunct6Shift), 465 466 VFNMACC_FUNCT6 = 0b101101, 467 RO_V_VFNMACC_VV = OP_FVV | (VFNMACC_FUNCT6 << kRvvFunct6Shift), 468 RO_V_VFNMACC_VF = OP_FVF | (VFNMACC_FUNCT6 << kRvvFunct6Shift), 469 470 VFMSAC_FUNCT6 = 0b101110, 471 RO_V_VFMSAC_VV = OP_FVV | (VFMSAC_FUNCT6 << kRvvFunct6Shift), 472 RO_V_VFMSAC_VF = OP_FVF | (VFMSAC_FUNCT6 << kRvvFunct6Shift), 473 474 VFNMSAC_FUNCT6 = 0b101111, 475 RO_V_VFNMSAC_VV = OP_FVV | (VFNMSAC_FUNCT6 << kRvvFunct6Shift), 476 RO_V_VFNMSAC_VF = OP_FVF | (VFNMSAC_FUNCT6 << kRvvFunct6Shift), 477 478 // Vector Widening Floating-Point Fused Multiply-Add Instructions 479 VFWMACC_FUNCT6 = 0b111100, 480 RO_V_VFWMACC_VV = OP_FVV | (VFWMACC_FUNCT6 << kRvvFunct6Shift), 481 RO_V_VFWMACC_VF = OP_FVF | (VFWMACC_FUNCT6 << kRvvFunct6Shift), 482 483 VFWNMACC_FUNCT6 = 0b111101, 484 RO_V_VFWNMACC_VV = OP_FVV | (VFWNMACC_FUNCT6 << kRvvFunct6Shift), 485 RO_V_VFWNMACC_VF = OP_FVF | (VFWNMACC_FUNCT6 << kRvvFunct6Shift), 486 487 VFWMSAC_FUNCT6 = 0b111110, 488 RO_V_VFWMSAC_VV = OP_FVV | (VFWMSAC_FUNCT6 << kRvvFunct6Shift), 489 RO_V_VFWMSAC_VF = OP_FVF | (VFWMSAC_FUNCT6 << kRvvFunct6Shift), 490 491 VFWNMSAC_FUNCT6 = 0b111111, 492 RO_V_VFWNMSAC_VV = OP_FVV | (VFWNMSAC_FUNCT6 << kRvvFunct6Shift), 493 RO_V_VFWNMSAC_VF = OP_FVF | (VFWNMSAC_FUNCT6 << kRvvFunct6Shift), 494 495 VNCLIP_FUNCT6 = 0b101111, 496 RO_V_VNCLIP_WV = OP_IVV | (VNCLIP_FUNCT6 << kRvvFunct6Shift), 497 RO_V_VNCLIP_WX = OP_IVX | (VNCLIP_FUNCT6 << kRvvFunct6Shift), 498 RO_V_VNCLIP_WI = OP_IVI | (VNCLIP_FUNCT6 << kRvvFunct6Shift), 499 500 VNCLIPU_FUNCT6 = 0b101110, 501 RO_V_VNCLIPU_WV = OP_IVV | (VNCLIPU_FUNCT6 << kRvvFunct6Shift), 502 RO_V_VNCLIPU_WX = OP_IVX | (VNCLIPU_FUNCT6 << kRvvFunct6Shift), 503 RO_V_VNCLIPU_WI = OP_IVI | (VNCLIPU_FUNCT6 << kRvvFunct6Shift), 504 }; 505 } // namespace jit 506 } // namespace js 507 508 #endif // jit_riscv64_constant_Constant_riscv64_v_h_