Constant-riscv-i.h (3565B)
1 // Copyright 2022 the V8 project authors. All rights reserved. 2 // Use of this source code is governed by a BSD-style license that can be 3 // found in the LICENSE file. 4 #ifndef jit_riscv64_constant_Constant_riscv64_i_h_ 5 #define jit_riscv64_constant_Constant_riscv64_i_h_ 6 #include "jit/riscv64/constant/Base-constant-riscv.h" 7 namespace js { 8 namespace jit { 9 10 enum OpcodeRISCV32I : uint32_t { 11 // Note use RO (RiscV Opcode) prefix 12 // RV32I Base Instruction Set 13 RO_LUI = LUI, 14 RO_AUIPC = AUIPC, 15 RO_JAL = JAL, 16 RO_JALR = JALR | (0b000 << kFunct3Shift), 17 RO_BEQ = BRANCH | (0b000 << kFunct3Shift), 18 RO_BNE = BRANCH | (0b001 << kFunct3Shift), 19 RO_BLT = BRANCH | (0b100 << kFunct3Shift), 20 RO_BGE = BRANCH | (0b101 << kFunct3Shift), 21 RO_BLTU = BRANCH | (0b110 << kFunct3Shift), 22 RO_BGEU = BRANCH | (0b111 << kFunct3Shift), 23 RO_LB = LOAD | (0b000 << kFunct3Shift), 24 RO_LH = LOAD | (0b001 << kFunct3Shift), 25 RO_LW = LOAD | (0b010 << kFunct3Shift), 26 RO_LBU = LOAD | (0b100 << kFunct3Shift), 27 RO_LHU = LOAD | (0b101 << kFunct3Shift), 28 RO_SB = STORE | (0b000 << kFunct3Shift), 29 RO_SH = STORE | (0b001 << kFunct3Shift), 30 RO_SW = STORE | (0b010 << kFunct3Shift), 31 RO_ADDI = OP_IMM | (0b000 << kFunct3Shift), 32 RO_SLTI = OP_IMM | (0b010 << kFunct3Shift), 33 RO_SLTIU = OP_IMM | (0b011 << kFunct3Shift), 34 RO_XORI = OP_IMM | (0b100 << kFunct3Shift), 35 RO_ORI = OP_IMM | (0b110 << kFunct3Shift), 36 RO_ANDI = OP_IMM | (0b111 << kFunct3Shift), 37 38 OP_SHL = 0b0010011 | (0b001 << kFunct3Shift), 39 RO_SLLI = OP_SHL | (0b000000 << kFunct6Shift), 40 41 OP_SHR = 0b0010011 | (0b101 << kFunct3Shift), 42 RO_SRLI = OP_SHR | (0b000000 << kFunct6Shift), 43 RO_SRAI = OP_SHR | (0b010000 << kFunct6Shift), 44 45 RO_ADD = OP | (0b000 << kFunct3Shift) | (0b0000000 << kFunct7Shift), 46 RO_SUB = OP | (0b000 << kFunct3Shift) | (0b0100000 << kFunct7Shift), 47 RO_SLL = OP | (0b001 << kFunct3Shift) | (0b0000000 << kFunct7Shift), 48 RO_SLT = OP | (0b010 << kFunct3Shift) | (0b0000000 << kFunct7Shift), 49 RO_SLTU = OP | (0b011 << kFunct3Shift) | (0b0000000 << kFunct7Shift), 50 RO_XOR = OP | (0b100 << kFunct3Shift) | (0b0000000 << kFunct7Shift), 51 RO_SRL = OP | (0b101 << kFunct3Shift) | (0b0000000 << kFunct7Shift), 52 RO_SRA = OP | (0b101 << kFunct3Shift) | (0b0100000 << kFunct7Shift), 53 RO_OR = OP | (0b110 << kFunct3Shift) | (0b0000000 << kFunct7Shift), 54 RO_AND = OP | (0b111 << kFunct3Shift) | (0b0000000 << kFunct7Shift), 55 RO_FENCE = MISC_MEM | (0b000 << kFunct3Shift), 56 RO_ECALL = SYSTEM | (0b000 << kFunct3Shift), 57 // RO_EBREAK = SYSTEM | (0b000 << kFunct3Shift), // Same as ECALL, use imm12 58 59 #if JS_CODEGEN_RISCV64 60 // RV64I Base Instruction Set (in addition to RV32I) 61 RO_LWU = LOAD | (0b110 << kFunct3Shift), 62 RO_LD = LOAD | (0b011 << kFunct3Shift), 63 RO_SD = STORE | (0b011 << kFunct3Shift), 64 RO_ADDIW = OP_IMM_32 | (0b000 << kFunct3Shift), 65 66 OP_SHLW = OP_IMM_32 | (0b001 << kFunct3Shift), 67 RO_SLLIW = OP_SHLW | (0b0000000 << kFunct7Shift), 68 OP_SHRW = OP_IMM_32 | (0b101 << kFunct3Shift), 69 RO_SRLIW = OP_SHRW | (0b0000000 << kFunct7Shift), 70 RO_SRAIW = OP_SHRW | (0b0100000 << kFunct7Shift), 71 72 RO_ADDW = OP_32 | (0b000 << kFunct3Shift) | (0b0000000 << kFunct7Shift), 73 RO_SUBW = OP_32 | (0b000 << kFunct3Shift) | (0b0100000 << kFunct7Shift), 74 RO_SLLW = OP_32 | (0b001 << kFunct3Shift) | (0b0000000 << kFunct7Shift), 75 RO_SRLW = OP_32 | (0b101 << kFunct3Shift) | (0b0000000 << kFunct7Shift), 76 RO_SRAW = OP_32 | (0b101 << kFunct3Shift) | (0b0100000 << kFunct7Shift), 77 #endif 78 }; 79 } // namespace jit 80 } // namespace js 81 82 #endif // jit_riscv64_constant_Constant_riscv64_i_h_