Cpu-vixl.h (10827B)
1 // Copyright 2014, VIXL authors 2 // All rights reserved. 3 // 4 // Redistribution and use in source and binary forms, with or without 5 // modification, are permitted provided that the following conditions are met: 6 // 7 // * Redistributions of source code must retain the above copyright notice, 8 // this list of conditions and the following disclaimer. 9 // * Redistributions in binary form must reproduce the above copyright notice, 10 // this list of conditions and the following disclaimer in the documentation 11 // and/or other materials provided with the distribution. 12 // * Neither the name of ARM Limited nor the names of its contributors may be 13 // used to endorse or promote products derived from this software without 14 // specific prior written permission. 15 // 16 // THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS CONTRIBUTORS "AS IS" AND 17 // ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 18 // WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 19 // DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE 20 // FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 21 // DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 22 // SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER 23 // CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 24 // OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 25 // OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 26 27 #ifndef VIXL_CPU_AARCH64_H 28 #define VIXL_CPU_AARCH64_H 29 30 #include "jit/arm64/vixl/Cpu-Features-vixl.h" 31 #include "jit/arm64/vixl/Globals-vixl.h" 32 33 #include "jit/arm64/vixl/Instructions-vixl.h" 34 35 #ifndef VIXL_INCLUDE_TARGET_AARCH64 36 // The supporting .cc file is only compiled when the A64 target is selected. 37 // Throw an explicit error now to avoid a harder-to-debug linker error later. 38 // 39 // These helpers _could_ work on any AArch64 host, even when generating AArch32 40 // code, but we don't support this because the available features may differ 41 // between AArch32 and AArch64 on the same platform, so basing AArch32 code 42 // generation on aarch64::CPU features is probably broken. 43 #error cpu-aarch64.h requires VIXL_INCLUDE_TARGET_AARCH64 (scons target=a64). 44 #endif 45 46 namespace vixl { 47 48 // A CPU ID register, for use with CPUFeatures::kIDRegisterEmulation. Fields 49 // specific to each register are described in relevant subclasses. 50 class IDRegister { 51 protected: 52 explicit IDRegister(uint64_t value = 0) : value_(value) {} 53 54 class Field { 55 public: 56 enum Type { kUnsigned, kSigned }; 57 58 static const int kMaxWidthInBits = 4; 59 60 // This needs to be constexpr so that fields have "constant initialisation". 61 // This avoids initialisation order problems when these values are used to 62 // (dynamically) initialise static variables, etc. 63 explicit constexpr Field(int lsb, 64 int bitWidth = kMaxWidthInBits, 65 Type type = kUnsigned) 66 : lsb_(lsb), bitWidth_(bitWidth), type_(type) {} 67 68 int GetWidthInBits() const { return bitWidth_; } 69 int GetLsb() const { return lsb_; } 70 int GetMsb() const { return lsb_ + GetWidthInBits() - 1; } 71 Type GetType() const { return type_; } 72 73 private: 74 int lsb_; 75 int bitWidth_; 76 Type type_; 77 }; 78 79 public: 80 // Extract the specified field, performing sign-extension for signed fields. 81 // This allows us to implement the 'value >= number' detection mechanism 82 // recommended by the Arm ARM, for both signed and unsigned fields. 83 int Get(Field field) const; 84 85 private: 86 uint64_t value_; 87 }; 88 89 class AA64PFR0 : public IDRegister { 90 public: 91 explicit AA64PFR0(uint64_t value) : IDRegister(value) {} 92 93 CPUFeatures GetCPUFeatures() const; 94 95 private: 96 static const Field kFP; 97 static const Field kAdvSIMD; 98 static const Field kRAS; 99 static const Field kSVE; 100 static const Field kDIT; 101 static const Field kCSV2; 102 static const Field kCSV3; 103 }; 104 105 class AA64PFR1 : public IDRegister { 106 public: 107 explicit AA64PFR1(uint64_t value) : IDRegister(value) {} 108 109 CPUFeatures GetCPUFeatures() const; 110 111 private: 112 static const Field kBT; 113 static const Field kSSBS; 114 static const Field kMTE; 115 static const Field kSME; 116 }; 117 118 class AA64ISAR0 : public IDRegister { 119 public: 120 explicit AA64ISAR0(uint64_t value) : IDRegister(value) {} 121 122 CPUFeatures GetCPUFeatures() const; 123 124 private: 125 static const Field kAES; 126 static const Field kSHA1; 127 static const Field kSHA2; 128 static const Field kCRC32; 129 static const Field kAtomic; 130 static const Field kRDM; 131 static const Field kSHA3; 132 static const Field kSM3; 133 static const Field kSM4; 134 static const Field kDP; 135 static const Field kFHM; 136 static const Field kTS; 137 static const Field kRNDR; 138 }; 139 140 class AA64ISAR1 : public IDRegister { 141 public: 142 explicit AA64ISAR1(uint64_t value) : IDRegister(value) {} 143 144 CPUFeatures GetCPUFeatures() const; 145 146 private: 147 static const Field kDPB; 148 static const Field kAPA; 149 static const Field kAPI; 150 static const Field kJSCVT; 151 static const Field kFCMA; 152 static const Field kLRCPC; 153 static const Field kGPA; 154 static const Field kGPI; 155 static const Field kFRINTTS; 156 static const Field kSB; 157 static const Field kSPECRES; 158 static const Field kBF16; 159 static const Field kDGH; 160 static const Field kI8MM; 161 }; 162 163 class AA64ISAR2 : public IDRegister { 164 public: 165 explicit AA64ISAR2(uint64_t value) : IDRegister(value) {} 166 167 CPUFeatures GetCPUFeatures() const; 168 169 private: 170 static const Field kWFXT; 171 static const Field kRPRES; 172 static const Field kMOPS; 173 static const Field kCSSC; 174 }; 175 176 class AA64MMFR0 : public IDRegister { 177 public: 178 explicit AA64MMFR0(uint64_t value) : IDRegister(value) {} 179 180 CPUFeatures GetCPUFeatures() const; 181 182 private: 183 static const Field kECV; 184 }; 185 186 class AA64MMFR1 : public IDRegister { 187 public: 188 explicit AA64MMFR1(uint64_t value) : IDRegister(value) {} 189 190 CPUFeatures GetCPUFeatures() const; 191 192 private: 193 static const Field kLO; 194 static const Field kAFP; 195 }; 196 197 class AA64MMFR2 : public IDRegister { 198 public: 199 explicit AA64MMFR2(uint64_t value) : IDRegister(value) {} 200 201 CPUFeatures GetCPUFeatures() const; 202 203 private: 204 static const Field kAT; 205 }; 206 207 class AA64ZFR0 : public IDRegister { 208 public: 209 explicit AA64ZFR0(uint64_t value) : IDRegister(value) {} 210 211 CPUFeatures GetCPUFeatures() const; 212 213 private: 214 static const Field kSVEver; 215 static const Field kAES; 216 static const Field kBitPerm; 217 static const Field kBF16; 218 static const Field kSHA3; 219 static const Field kSM4; 220 static const Field kI8MM; 221 static const Field kF32MM; 222 static const Field kF64MM; 223 }; 224 225 class AA64SMFR0 : public IDRegister { 226 public: 227 explicit AA64SMFR0(uint64_t value) : IDRegister(value) {} 228 229 CPUFeatures GetCPUFeatures() const; 230 231 private: 232 static const Field kSMEf32f32; 233 static const Field kSMEb16f32; 234 static const Field kSMEf16f32; 235 static const Field kSMEi8i32; 236 static const Field kSMEf64f64; 237 static const Field kSMEi16i64; 238 static const Field kSMEfa64; 239 }; 240 241 class CPU { 242 public: 243 // Initialise CPU support. 244 static void SetUp(); 245 246 // Ensures the data at a given address and with a given size is the same for 247 // the I and D caches. I and D caches are not automatically coherent on ARM 248 // so this operation is required before any dynamically generated code can 249 // safely run. 250 static void EnsureIAndDCacheCoherency(void* address, size_t length); 251 252 // Flush the local instruction pipeline, forcing a reload of any instructions 253 // beyond this barrier from the icache. 254 static void FlushExecutionContext(); 255 256 // Read and interpret the ID registers. This requires 257 // CPUFeatures::kIDRegisterEmulation, and therefore cannot be called on 258 // non-AArch64 platforms. 259 static CPUFeatures InferCPUFeaturesFromIDRegisters(); 260 261 // Read and interpret CPUFeatures reported by the OS. Failed queries (or 262 // unsupported platforms) return an empty list. Note that this is 263 // indistinguishable from a successful query on a platform that advertises no 264 // features. 265 // 266 // Non-AArch64 hosts are considered to be unsupported platforms, and this 267 // function returns an empty list. 268 static CPUFeatures InferCPUFeaturesFromOS( 269 CPUFeatures::QueryIDRegistersOption option = 270 CPUFeatures::kQueryIDRegistersIfAvailable); 271 272 // Query the SVE vector length. This requires CPUFeatures::kSVE. 273 static int ReadSVEVectorLengthInBits(); 274 275 // Handle tagged pointers. 276 template <typename T> 277 static T SetPointerTag(T pointer, uint64_t tag) { 278 VIXL_ASSERT(IsUintN(kAddressTagWidth, tag)); 279 280 // Use C-style casts to get static_cast behaviour for integral types (T), 281 // and reinterpret_cast behaviour for other types. 282 283 uint64_t raw = (uint64_t)pointer; 284 VIXL_STATIC_ASSERT(sizeof(pointer) == sizeof(raw)); 285 286 raw = (raw & ~kAddressTagMask) | (tag << kAddressTagOffset); 287 return (T)raw; 288 } 289 290 template <typename T> 291 static uint64_t GetPointerTag(T pointer) { 292 // Use C-style casts to get static_cast behaviour for integral types (T), 293 // and reinterpret_cast behaviour for other types. 294 295 uint64_t raw = (uint64_t)pointer; 296 VIXL_STATIC_ASSERT(sizeof(pointer) == sizeof(raw)); 297 298 return (raw & kAddressTagMask) >> kAddressTagOffset; 299 } 300 301 private: 302 #define VIXL_AARCH64_ID_REG_LIST(V) \ 303 V(AA64PFR0, "ID_AA64PFR0_EL1") \ 304 V(AA64PFR1, "ID_AA64PFR1_EL1") \ 305 V(AA64ISAR0, "ID_AA64ISAR0_EL1") \ 306 V(AA64ISAR1, "ID_AA64ISAR1_EL1") \ 307 V(AA64MMFR0, "ID_AA64MMFR0_EL1") \ 308 V(AA64MMFR1, "ID_AA64MMFR1_EL1") \ 309 /* These registers are RES0 in the baseline Arm8.0. We can always safely */ \ 310 /* read them, but some compilers don't accept the symbolic names. */ \ 311 V(AA64SMFR0, "S3_0_C0_C4_5") \ 312 V(AA64ISAR2, "S3_0_C0_C6_2") \ 313 V(AA64MMFR2, "S3_0_C0_C7_2") \ 314 V(AA64ZFR0, "S3_0_C0_C4_4") 315 316 #define VIXL_READ_ID_REG(NAME, MRS_ARG) static NAME Read##NAME(); 317 // On native AArch64 platforms, read the named CPU ID registers. These require 318 // CPUFeatures::kIDRegisterEmulation, and should not be called on non-AArch64 319 // platforms. 320 VIXL_AARCH64_ID_REG_LIST(VIXL_READ_ID_REG) 321 #undef VIXL_READ_ID_REG 322 323 // Return the content of the cache type register. 324 static uint32_t GetCacheType(); 325 326 // I and D cache line size in bytes. 327 static unsigned icache_line_size_; 328 static unsigned dcache_line_size_; 329 }; 330 331 } // namespace vixl 332 333 #endif // VIXL_CPU_AARCH64_H