bug1946618.js (2593B)
1 // |jit-test| --setpref=wasm_relaxed_simd=true; skip-if: !wasmRelaxedSimdEnabled() 2 3 // Relaxed simd allows its operations to produce implementation-specific 4 // results as carefully described by the spec. That's OK; however we require 5 // that baseline and Ion produce the same results. Hence what is important 6 // about this test program is not the results directly, but that a baseline and 7 // Ion run produce the same results. Since we have no way to directly test 8 // that, this test case at least hardwires results and expects them to be the 9 // same regardless of which compiler is used. 10 // 11 // For each `op`, "variant1" uses arguments 4 x 0x0000'0000 and 4 x 12 // 0xFFFF'FFFF, and "variant2" has the args the other way around. 13 // 14 // These tests are necessary because 0xFFFF'FFFF is a negative NaN, and the 15 // underlying Intel instructions are sensitive to operand ordering in the case 16 // where the input (lanes) hold NaNs. 17 18 for (let op of ["f32x4.relaxed_min", "f32x4.relaxed_max", 19 "f64x2.relaxed_min", "f64x2.relaxed_max"]) { 20 const t = ` 21 (module 22 (func (export "variant1") (result i32) 23 (i32.const 0) i8x16.splat 24 (i32.const 0) i8x16.splat 25 (i32.const 0) i8x16.splat 26 i32x4.eq 27 ;; stack top = 4 x 0xFFFF'FFFF ; stack top-1 = 4 x 0x0000'0000 28 ` + op + ` 29 i8x16.bitmask 30 ) 31 (func (export "variant2") (result i32) 32 (i32.const 0) i8x16.splat 33 (i32.const 0) i8x16.splat 34 i32x4.eq 35 (i32.const 0) i8x16.splat 36 ;; stack top = 4 x 0x0000'0000 ; stack top-1 = 4 x 0xFFFF'FFFF 37 ` + op + ` 38 i8x16.bitmask 39 ) 40 ) 41 `; 42 43 let i = 44 new WebAssembly.Instance(new WebAssembly.Module(wasmTextToBinary(t))); 45 // To reiterate comments above, we don't care what `result1` and `result2` 46 // are (although it would be very strange if they had any value other than 47 // zero or 65535). We care only that we get the same values on Ion and 48 // baseline. 49 let result1 = i.exports.variant1(); 50 let result2 = i.exports.variant2(); 51 if (getBuildConfiguration("arm64")) { 52 // The relaxed_min/max operation appears to propagate NaNs symmetrically 53 // from either arg 54 assertEq(result1, 65535); 55 assertEq(result2, 65535); 56 } else { 57 // x86_32 or x86_64, presumably. What happens when one of the args 58 // contains a NaN depends on which arg it is. See Intel documentation on 59 // `minps`/`maxps`. 60 assertEq(result1, 65535); 61 assertEq(result2, 0); 62 } 63 }