vhdl.vim (9658B)
1 " Vim syntax file 2 " Language: VHDL [VHSIC (Very High Speed Integrated Circuit) Hardware Description Language] 3 " Maintainer: Daniel Kho <daniel.kho@logik.haus> 4 " Previous Maintainer: Czo <Olivier.Sirol@lip6.fr> 5 " Credits: Stephan Hegel <stephan.hegel@snc.siemens.com.cn> 6 " Last Changed: 2020 Apr 04 by Daniel Kho 7 8 " quit when a syntax file was already loaded 9 if exists("b:current_syntax") 10 finish 11 endif 12 13 let s:cpo_save = &cpo 14 set cpo&vim 15 16 " case is not significant 17 syn case ignore 18 19 " VHDL 1076-2019 keywords 20 syn keyword vhdlStatement access after alias all 21 syn keyword vhdlStatement architecture array attribute 22 syn keyword vhdlStatement assert assume 23 syn keyword vhdlStatement begin block body buffer bus 24 syn keyword vhdlStatement case component configuration constant 25 syn keyword vhdlStatement context cover 26 syn keyword vhdlStatement default disconnect downto 27 syn keyword vhdlStatement elsif end entity exit 28 syn keyword vhdlStatement file for function 29 syn keyword vhdlStatement fairness force 30 syn keyword vhdlStatement generate generic group guarded 31 syn keyword vhdlStatement impure in inertial inout is 32 syn keyword vhdlStatement label library linkage literal loop 33 syn keyword vhdlStatement map 34 syn keyword vhdlStatement new next null 35 syn keyword vhdlStatement of on open others out 36 syn keyword vhdlStatement package port postponed procedure process pure 37 syn keyword vhdlStatement parameter property protected private 38 syn keyword vhdlStatement range record register reject report return 39 syn keyword vhdlStatement release restrict 40 syn keyword vhdlStatement select severity signal shared subtype 41 syn keyword vhdlStatement sequence strong 42 syn keyword vhdlStatement then to transport type 43 syn keyword vhdlStatement unaffected units until use 44 syn keyword vhdlStatement variable view 45 syn keyword vhdlStatement vpkg vmode vprop vunit 46 syn keyword vhdlStatement wait when while with 47 48 " VHDL predefined severity levels 49 syn keyword vhdlAttribute note warning error failure 50 51 " Linting of conditionals. 52 syn match vhdlStatement "\<\(if\|else\)\>" 53 syn match vhdlError "\<else\s\+if\>" 54 55 " Types and type qualifiers 56 " Predefined standard VHDL types 57 syn match vhdlType "\<bit\>\'\=" 58 syn match vhdlType "\<boolean\>\'\=" 59 syn match vhdlType "\<natural\>\'\=" 60 syn match vhdlType "\<positive\>\'\=" 61 syn match vhdlType "\<integer\>\'\=" 62 syn match vhdlType "\<real\>\'\=" 63 syn match vhdlType "\<time\>\'\=" 64 65 syn match vhdlType "\<bit_vector\>\'\=" 66 syn match vhdlType "\<boolean_vector\>\'\=" 67 syn match vhdlType "\<integer_vector\>\'\=" 68 syn match vhdlType "\<real_vector\>\'\=" 69 syn match vhdlType "\<time_vector\>\'\=" 70 71 syn match vhdlType "\<character\>\'\=" 72 syn match vhdlType "\<string\>\'\=" 73 syn keyword vhdlType line text side width 74 75 " Predefined standard IEEE VHDL types 76 syn match vhdlType "\<std_ulogic\>\'\=" 77 syn match vhdlType "\<std_logic\>\'\=" 78 syn match vhdlType "\<std_ulogic_vector\>\'\=" 79 syn match vhdlType "\<std_logic_vector\>\'\=" 80 syn match vhdlType "\<unresolved_signed\>\'\=" 81 syn match vhdlType "\<unresolved_unsigned\>\'\=" 82 syn match vhdlType "\<u_signed\>\'\=" 83 syn match vhdlType "\<u_unsigned\>\'\=" 84 syn match vhdlType "\<signed\>\'\=" 85 syn match vhdlType "\<unsigned\>\'\=" 86 87 88 " array attributes 89 syn match vhdlAttribute "\'high" 90 syn match vhdlAttribute "\'left" 91 syn match vhdlAttribute "\'length" 92 syn match vhdlAttribute "\'low" 93 syn match vhdlAttribute "\'range" 94 syn match vhdlAttribute "\'reverse_range" 95 syn match vhdlAttribute "\'right" 96 syn match vhdlAttribute "\'ascending" 97 " block attributes 98 syn match vhdlAttribute "\'simple_name" 99 syn match vhdlAttribute "\'instance_name" 100 syn match vhdlAttribute "\'path_name" 101 syn match vhdlAttribute "\'foreign" " VHPI 102 " signal attribute 103 syn match vhdlAttribute "\'active" 104 syn match vhdlAttribute "\'delayed" 105 syn match vhdlAttribute "\'event" 106 syn match vhdlAttribute "\'last_active" 107 syn match vhdlAttribute "\'last_event" 108 syn match vhdlAttribute "\'last_value" 109 syn match vhdlAttribute "\'quiet" 110 syn match vhdlAttribute "\'stable" 111 syn match vhdlAttribute "\'transaction" 112 syn match vhdlAttribute "\'driving" 113 syn match vhdlAttribute "\'driving_value" 114 " type attributes 115 syn match vhdlAttribute "\'base" 116 syn match vhdlAttribute "\'subtype" 117 syn match vhdlAttribute "\'element" 118 syn match vhdlAttribute "\'leftof" 119 syn match vhdlAttribute "\'pos" 120 syn match vhdlAttribute "\'pred" 121 syn match vhdlAttribute "\'rightof" 122 syn match vhdlAttribute "\'succ" 123 syn match vhdlAttribute "\'val" 124 syn match vhdlAttribute "\'image" 125 syn match vhdlAttribute "\'value" 126 " VHDL-2019 interface attribute 127 syn match vhdlAttribute "\'converse" 128 129 syn keyword vhdlBoolean true false 130 131 " for this vector values case is significant 132 syn case match 133 " Values for standard VHDL types 134 syn match vhdlVector "\'[0L1HXWZU\-\?]\'" 135 syn case ignore 136 137 syn match vhdlVector "B\"[01_]\+\"" 138 syn match vhdlVector "O\"[0-7_]\+\"" 139 syn match vhdlVector "X\"[0-9a-f_]\+\"" 140 syn match vhdlCharacter "'.'" 141 syn region vhdlString start=+"+ end=+"+ 142 143 " floating numbers 144 syn match vhdlNumber "-\=\<\d\+\.\d\+\(E[+\-]\=\d\+\)\>" 145 syn match vhdlNumber "-\=\<\d\+\.\d\+\>" 146 syn match vhdlNumber "0*2#[01_]\+\.[01_]\+#\(E[+\-]\=\d\+\)\=" 147 syn match vhdlNumber "0*16#[0-9a-f_]\+\.[0-9a-f_]\+#\(E[+\-]\=\d\+\)\=" 148 " integer numbers 149 syn match vhdlNumber "-\=\<\d\+\(E[+\-]\=\d\+\)\>" 150 syn match vhdlNumber "-\=\<\d\+\>" 151 syn match vhdlNumber "0*2#[01_]\+#\(E[+\-]\=\d\+\)\=" 152 syn match vhdlNumber "0*16#[0-9a-f_]\+#\(E[+\-]\=\d\+\)\=" 153 154 " operators 155 syn keyword vhdlOperator and nand or nor xor xnor 156 syn keyword vhdlOperator rol ror sla sll sra srl 157 syn keyword vhdlOperator mod rem abs not 158 159 " Concatenation and math operators 160 syn match vhdlOperator "&\|+\|-\|\*\|\/" 161 162 " Equality and comparison operators 163 syn match vhdlOperator "=\|\/=\|>\|<\|>=" 164 165 " Assignment operators 166 syn match vhdlOperator "<=\|:=" 167 syn match vhdlOperator "=>" 168 169 " VHDL-202x concurrent signal association (spaceship) operator 170 syn match vhdlOperator "<=>" 171 172 " VHDL-2008 conversion, matching equality/non-equality operators 173 syn match vhdlOperator "??\|?=\|?\/=\|?<\|?<=\|?>\|?>=" 174 175 " VHDL-2008 external names 176 syn match vhdlOperator "<<\|>>" 177 178 " Linting for illegal operators 179 " '=' 180 syn match vhdlError "\(=\)[<=&+\-\*\/\\]\+" 181 syn match vhdlError "[=&+\-\*\\]\+\(=\)" 182 " '>', '<' 183 " Allow external names: '<< ... >>' 184 syn match vhdlError "\(>\)[<&+\-\/\\]\+" 185 syn match vhdlError "[&+\-\/\\]\+\(>\)" 186 syn match vhdlError "\(<\)[&+\-\/\\]\+" 187 syn match vhdlError "[>=&+\-\/\\]\+\(<\)" 188 " Covers most operators 189 " support negative sign after operators. E.g. q<=-b; 190 " Supports VHDL-202x spaceship (concurrent simple signal association). 191 syn match vhdlError "\(<=\)[<=&+\*\\?:]\+" 192 syn match vhdlError "[>=&+\-\*\\:]\+\(=>\)" 193 syn match vhdlError "\(&\|+\|\-\|\*\*\|\/=\|??\|?=\|?\/=\|?<=\|?>=\|>=\|:=\|=>\)[<>=&+\*\\?:]\+" 194 syn match vhdlError "[<>=&+\-\*\\:]\+\(&\|+\|\*\*\|\/=\|??\|?=\|?\/=\|?<\|?<=\|?>\|?>=\|>=\|<=\|:=\)" 195 syn match vhdlError "\(?<\|?>\)[<>&+\*\/\\?:]\+" 196 syn match vhdlError "\(<<\|>>\)[<>&+\*\/\\?:]\+" 197 198 "syn match vhdlError "[?]\+\(&\|+\|\-\|\*\*\|??\|?=\|?\/=\|?<\|?<=\|?>\|?>=\|:=\|=>\)" 199 " '/' 200 syn match vhdlError "\(\/\)[<>&+\-\*\/\\?:]\+" 201 syn match vhdlError "[<>=&+\-\*\/\\:]\+\(\/\)" 202 203 syn match vhdlSpecial "<>" 204 syn match vhdlSpecial "[().,;]" 205 206 207 " time 208 syn match vhdlTime "\<\d\+\s\+\(\([fpnum]s\)\|\(sec\)\|\(min\)\|\(hr\)\)\>" 209 syn match vhdlTime "\<\d\+\.\d\+\s\+\(\([fpnum]s\)\|\(sec\)\|\(min\)\|\(hr\)\)\>" 210 211 syn case match 212 syn keyword vhdlTodo contained TODO NOTE 213 syn keyword vhdlFixme contained FIXME 214 syn case ignore 215 216 syn region vhdlComment start="/\*" end="\*/" contains=vhdlTodo,vhdlFixme,@Spell 217 syn match vhdlComment "\(^\|\s\)--.*" contains=vhdlTodo,vhdlFixme,@Spell 218 219 " Standard IEEE P1076.6 preprocessor directives (metacomments). 220 syn match vhdlPreProc "/\*\s*rtl_synthesis\s\+\(on\|off\)\s*\*/" 221 syn match vhdlPreProc "\(^\|\s\)--\s*rtl_synthesis\s\+\(on\|off\)\s*" 222 syn match vhdlPreProc "/\*\s*rtl_syn\s\+\(on\|off\)\s*\*/" 223 syn match vhdlPreProc "\(^\|\s\)--\s*rtl_syn\s\+\(on\|off\)\s*" 224 225 " Industry-standard directives. These are not standard VHDL, but are commonly 226 " used in the industry. 227 syn match vhdlPreProc "/\*\s*synthesis\s\+translate_\(on\|off\)\s*\*/" 228 "syn match vhdlPreProc "/\*\s*simulation\s\+translate_\(on\|off\)\s*\*/" 229 syn match vhdlPreProc "/\*\s*pragma\s\+translate_\(on\|off\)\s*\*/" 230 syn match vhdlPreProc "/\*\s*pragma\s\+synthesis_\(on\|off\)\s*\*/" 231 syn match vhdlPreProc "/\*\s*synopsys\s\+translate_\(on\|off\)\s*\*/" 232 233 syn match vhdlPreProc "\(^\|\s\)--\s*synthesis\s\+translate_\(on\|off\)\s*" 234 "syn match vhdlPreProc "\(^\|\s\)--\s*simulation\s\+translate_\(on\|off\)\s*" 235 syn match vhdlPreProc "\(^\|\s\)--\s*pragma\s\+translate_\(on\|off\)\s*" 236 syn match vhdlPreProc "\(^\|\s\)--\s*pragma\s\+synthesis_\(on\|off\)\s*" 237 syn match vhdlPreProc "\(^\|\s\)--\s*synopsys\s\+translate_\(on\|off\)\s*" 238 239 "Modify the following as needed. The trade-off is performance versus functionality. 240 syn sync minlines=600 241 242 " Define the default highlighting. 243 " Only when an item doesn't have highlighting yet 244 245 hi def link vhdlSpecial Special 246 hi def link vhdlStatement Statement 247 hi def link vhdlCharacter Character 248 hi def link vhdlString String 249 hi def link vhdlVector Number 250 hi def link vhdlBoolean Number 251 hi def link vhdlTodo Todo 252 hi def link vhdlFixme Fixme 253 hi def link vhdlComment Comment 254 hi def link vhdlNumber Number 255 hi def link vhdlTime Number 256 hi def link vhdlType Type 257 hi def link vhdlOperator Operator 258 hi def link vhdlError Error 259 hi def link vhdlAttribute Special 260 hi def link vhdlPreProc PreProc 261 262 263 let b:current_syntax = "vhdl" 264 265 let &cpo = s:cpo_save 266 unlet s:cpo_save 267 268 " vim: ts=8