verilog.vim (5055B)
1 " Vim syntax file 2 " Language: Verilog 3 " Maintainer: Mun Johl <Mun.Johl@emulex.com> 4 " Last Update: Wed Jul 20 16:04:19 PDT 2011 5 6 " quit when a syntax file was already loaded 7 if exists("b:current_syntax") 8 finish 9 endif 10 11 " Set the local value of the 'iskeyword' option. 12 " NOTE: '?' was added so that verilogNumber would be processed correctly when 13 " '?' is the last character of the number. 14 setlocal iskeyword=@,48-57,63,_,192-255 15 16 " A bunch of useful Verilog keywords 17 18 syn keyword verilogStatement always and assign automatic buf 19 syn keyword verilogStatement bufif0 bufif1 cell cmos 20 syn keyword verilogStatement config deassign defparam design 21 syn keyword verilogStatement disable edge endconfig 22 syn keyword verilogStatement endfunction endgenerate endmodule 23 syn keyword verilogStatement endprimitive endspecify endtable endtask 24 syn keyword verilogStatement event force function 25 syn keyword verilogStatement generate genvar highz0 highz1 ifnone 26 syn keyword verilogStatement incdir include initial inout input 27 syn keyword verilogStatement instance integer large liblist 28 syn keyword verilogStatement library localparam macromodule medium 29 syn keyword verilogStatement module nand negedge nmos nor 30 syn keyword verilogStatement noshowcancelled not notif0 notif1 or 31 syn keyword verilogStatement output parameter pmos posedge primitive 32 syn keyword verilogStatement pull0 pull1 pulldown pullup 33 syn keyword verilogStatement pulsestyle_onevent pulsestyle_ondetect 34 syn keyword verilogStatement rcmos real realtime reg release 35 syn keyword verilogStatement rnmos rpmos rtran rtranif0 rtranif1 36 syn keyword verilogStatement scalared showcancelled signed small 37 syn keyword verilogStatement specify specparam strong0 strong1 38 syn keyword verilogStatement supply0 supply1 table task time tran 39 syn keyword verilogStatement tranif0 tranif1 tri tri0 tri1 triand 40 syn keyword verilogStatement trior trireg unsigned use vectored wait 41 syn keyword verilogStatement wand weak0 weak1 wire wor xnor xor 42 syn keyword verilogLabel begin end fork join 43 syn keyword verilogConditional if else case casex casez default endcase 44 syn keyword verilogRepeat forever repeat while for 45 46 syn keyword verilogTodo contained TODO FIXME 47 48 syn match verilogOperator "[&|~><!)(*#%@+/=?:;}{,.\^\-\[\]]" 49 50 syn region verilogComment start="/\*" end="\*/" contains=verilogTodo,@Spell 51 syn match verilogComment "//.*" contains=verilogTodo,@Spell 52 53 "syn match verilogGlobal "`[a-zA-Z0-9_]\+\>" 54 syn match verilogGlobal "`celldefine" 55 syn match verilogGlobal "`default_nettype" 56 syn match verilogGlobal "`define" 57 syn match verilogGlobal "`else" 58 syn match verilogGlobal "`elsif" 59 syn match verilogGlobal "`endcelldefine" 60 syn match verilogGlobal "`endif" 61 syn match verilogGlobal "`ifdef" 62 syn match verilogGlobal "`ifndef" 63 syn match verilogGlobal "`include" 64 syn match verilogGlobal "`line" 65 syn match verilogGlobal "`nounconnected_drive" 66 syn match verilogGlobal "`resetall" 67 syn match verilogGlobal "`timescale" 68 syn match verilogGlobal "`unconnected_drive" 69 syn match verilogGlobal "`undef" 70 syn match verilogGlobal "$[a-zA-Z0-9_]\+\>" 71 72 syn match verilogConstant "\<[A-Z][A-Z0-9_]\+\>" 73 74 syn match verilogNumber "\(\<\d\+\|\)'[sS]\?[bB]\s*[0-1_xXzZ?]\+\>" 75 syn match verilogNumber "\(\<\d\+\|\)'[sS]\?[oO]\s*[0-7_xXzZ?]\+\>" 76 syn match verilogNumber "\(\<\d\+\|\)'[sS]\?[dD]\s*[0-9_xXzZ?]\+\>" 77 syn match verilogNumber "\(\<\d\+\|\)'[sS]\?[hH]\s*[0-9a-fA-F_xXzZ?]\+\>" 78 syn match verilogNumber "\<[+-]\=[0-9_]\+\(\.[0-9_]*\|\)\(e[0-9_]*\|\)\>" 79 80 syn region verilogString start=+"+ skip=+\\"+ end=+"+ contains=verilogEscape,@Spell 81 syn match verilogEscape +\\[nt"\\]+ contained 82 syn match verilogEscape "\\\o\o\=\o\=" contained 83 84 " Directives 85 syn match verilogDirective "//\s*synopsys\>.*$" 86 syn region verilogDirective start="/\*\s*synopsys\>" end="\*/" 87 syn region verilogDirective start="//\s*synopsys dc_script_begin\>" end="//\s*synopsys dc_script_end\>" 88 89 syn match verilogDirective "//\s*\$s\>.*$" 90 syn region verilogDirective start="/\*\s*\$s\>" end="\*/" 91 syn region verilogDirective start="//\s*\$s dc_script_begin\>" end="//\s*\$s dc_script_end\>" 92 93 "Modify the following as needed. The trade-off is performance versus 94 "functionality. 95 syn sync minlines=50 96 97 " Define the default highlighting. 98 " Only when an item doesn't have highlighting yet 99 100 " The default highlighting. 101 hi def link verilogCharacter Character 102 hi def link verilogConditional Conditional 103 hi def link verilogRepeat Repeat 104 hi def link verilogString String 105 hi def link verilogTodo Todo 106 hi def link verilogComment Comment 107 hi def link verilogConstant Constant 108 hi def link verilogLabel Label 109 hi def link verilogNumber Number 110 hi def link verilogOperator Special 111 hi def link verilogStatement Statement 112 hi def link verilogGlobal Define 113 hi def link verilogDirective SpecialComment 114 hi def link verilogEscape Special 115 116 117 let b:current_syntax = "verilog" 118 119 " vim: ts=8