systemverilog.vim (3755B)
1 " Vim syntax file 2 " Language: SystemVerilog 3 " Maintainer: kocha <kocha.lsifrontend@gmail.com> 4 " Last Change: 12-Aug-2013. 5 " 2025 Aug 20 by Vim project: Add IEE1800-2023 block #18056 6 7 " quit when a syntax file was already loaded 8 if exists("b:current_syntax") 9 finish 10 endif 11 12 " Read in Verilog syntax files 13 runtime! syntax/verilog.vim 14 unlet b:current_syntax 15 16 " IEEE1800-2005 17 syn keyword systemverilogStatement always_comb always_ff always_latch 18 syn keyword systemverilogStatement class endclass new 19 syn keyword systemverilogStatement virtual local const protected 20 syn keyword systemverilogStatement package endpackage 21 syn keyword systemverilogStatement rand randc constraint randomize 22 syn keyword systemverilogStatement with inside dist 23 syn keyword systemverilogStatement sequence endsequence randsequence 24 syn keyword systemverilogStatement srandom 25 syn keyword systemverilogStatement logic bit byte 26 syn keyword systemverilogStatement int longint shortint 27 syn keyword systemverilogStatement struct packed 28 syn keyword systemverilogStatement final 29 syn keyword systemverilogStatement import export 30 syn keyword systemverilogStatement context pure 31 syn keyword systemverilogStatement void shortreal chandle string 32 syn keyword systemverilogStatement clocking endclocking iff 33 syn keyword systemverilogStatement interface endinterface modport 34 syn keyword systemverilogStatement cover covergroup coverpoint endgroup 35 syn keyword systemverilogStatement property endproperty 36 syn keyword systemverilogStatement program endprogram 37 syn keyword systemverilogStatement bins binsof illegal_bins ignore_bins 38 syn keyword systemverilogStatement alias matches solve static assert 39 syn keyword systemverilogStatement assume super before expect bind 40 syn keyword systemverilogStatement extends null tagged extern this 41 syn keyword systemverilogStatement first_match throughout timeprecision 42 syn keyword systemverilogStatement timeunit type union 43 syn keyword systemverilogStatement uwire var cross ref wait_order intersect 44 syn keyword systemverilogStatement wildcard within 45 46 syn keyword systemverilogTypeDef typedef enum 47 48 syn keyword systemverilogConditional randcase 49 syn keyword systemverilogConditional unique priority 50 51 syn keyword systemverilogRepeat return break continue 52 syn keyword systemverilogRepeat do foreach 53 54 syn keyword systemverilogLabel join_any join_none forkjoin 55 56 " IEEE1800-2009 add 57 syn keyword systemverilogStatement checker endchecker 58 syn keyword systemverilogStatement accept_on reject_on 59 syn keyword systemverilogStatement sync_accept_on sync_reject_on 60 syn keyword systemverilogStatement eventually nexttime until until_with 61 syn keyword systemverilogStatement s_always s_eventually s_nexttime s_until s_until_with 62 syn keyword systemverilogStatement let untyped 63 syn keyword systemverilogStatement strong weak 64 syn keyword systemverilogStatement restrict global implies 65 66 syn keyword systemverilogConditional unique0 67 68 " IEEE1800-2012 add 69 syn keyword systemverilogStatement implements 70 syn keyword systemverilogStatement interconnect soft nettype 71 72 " IEEE1800-2023 add 73 syn region systemverilogBlockString start=+"""+ end=+"""+ contains=verilogEscape,@Spell 74 75 " Define the default highlighting. 76 77 " The default highlighting. 78 hi def link systemverilogStatement Statement 79 hi def link systemverilogTypeDef TypeDef 80 hi def link systemverilogConditional Conditional 81 hi def link systemverilogRepeat Repeat 82 hi def link systemverilogLabel Label 83 hi def link systemverilogGlobal Define 84 hi def link systemverilogNumber Number 85 hi def link systemverilogBlockString String 86 87 88 let b:current_syntax = "systemverilog" 89 90 " vim: ts=8